Abstract
BW = f s/(2 OSR). As this equation indicates, wideband ΣΔ ADCs having bandwidths in the hundreds of MHz require clock frequencies in the GHz range even to obtain a relatively low OSR of ten. In such low-OSR systems, MASH architectures achieve better power efficiency than traditional single-loop ΣΔ ADCs. Nanometer CMOS process technologies enable continuous-time ΣΔ ADCs operating at GHz clock frequencies. However, the combination of continuous-time and low-OSR at a GHz clock frequency presents new challenges. In this paper, ΣΔ ADCs including the traditional single-loop and MASH, are reviewed in the context of wideband wireless applications with out-of-band blockers. A unique circuit block in continuous-time MASH, a continuous-time residue generation circuit, is discussed in detail. Two wideband MASH implementations in a 28 nm CMOS process are compared and their properties and performances are discussed based on the architectural differences.
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References
R. Schreier, G.C. Temes, Understanding Delta-Sigma Data Converters (Wiley-IEEE Press, New York, 2005)
T. Caldwell, D. Alldred, R. Schreier, H. Shibata, Y. Dong, Advances in high-speed continuous-time ΣΔ modulators, in 2014 IEEE Proceedings of the Custom Integrated Circuits Conference, pp. 1–8, 2014
M. Bolatkale, L.J. Breems, R. Rutten, K.A.A. Makinwa, A 4GHz continuous-time ADC with 70dB DR and 74dBFS THD in 125MHz BW. IEEE J. Solid State Circuits 46(12), 2857–2868 (2011)
H. Shibata, R. Schreier, W. Yang, A. Shaikh, D. Paterson, T. Caldwell, D. Alldred, P.W. Lai, A DC-to-1GHz tunable RF ADC achieving DR=74dB and BW=150MHz at f 0=450MHz using 550mW. IEEE J. Solid State Circuits 47(12), 2888–2897 (2012)
Y. Dong, W. Yang, R. Schreier, A. Sheikholeslami, S. Korrapati, A continuous-time 0-3 MASH ADC achieving 88dB DR with 53MHz BW in 28nm CMOS. IEEE J. Solid State Circuits 49(12), 2868–2877 (2014)
Y. Dong, J. Zhao, W. Yang, T. Caldwell, H. Shibata, R. Schreier, Q. Meng, J. Silva, D. Paterson, J. Gealow, A 930mW 69dB DR 465MHz BW CT 1-2 MASH ADC in 28nm CMOS, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 278–279, Feb 2016
R. Schreier, Delta Sigma Toolbox, Matlab Central, http://www.mathworks.com/matlabcentral/fileexchange/19-delta-sigma-toolbox, 2016
K. Philips, P. Nuijten, R. Roovers, A. Roermund, F. Chavero, M. Pallarés, A. Torralba, A continuous-time ΣΔ ADC with increased immunity to interferers. IEEE J. Solid State Circuits 39, 2170–2177 (2005)
L.J. Breems, R. Rutten, G. Wetzker, A cascaded continuous-time modulator with 67-dB dynamic range in 10MHz bandwidth. IEEE J. Solid State Circuits 39(12), 2152–2160 (2004)
L.J. Breems, R. Rutten, R. Veldhoven, G. Weide, A 56mW continuous-time quadrature cascaded ΣΔ modulator with 77dB DR in a near Zero-IF 20MHz band. IEEE J. Solid State Circuits 42(12), 2696–2705 (2007)
Y. Matsuya, K. Uchimura, A. Iwata, T. Kobayashi, M. Ishikawa, T. Yoshitome, A 16-bit oversampling A-to-D conversion technology using triple integration noise shaping. IEEE J. Solid State Circuits SC-22(6), 921–979 (1987)
J. Steensgaard, High-Performance Data Converters, Chapter 9, Ph.D. Thesis, The Technical University of Denmark, Lyngby, Denmark, 1999
A. Gharbiya, D.A. Johns, A 12-bit 3.125MHz bandwidth 0-3 MASH Delta-Sigma modulator. IEEE J. Solid State Circuits 44(7), 2010–2018 (2009)
Y. Chae, K. Souri, K.A.A. Makinwa, A 6.3μW 20bit incremental zoom-ADC with 6ppm INL and 1μV offset. IEEE J. Solid State Circuits 48(12), 3019–3027 (2013)
B. Gonen, F. Sebastiano, R. Veldhoven, K.A.A. Makinwa, A 1.65mW 0.16mm2 dynamic zoom-ADC with 107.6dB DR in 20kHz BW, in IEEE International Solid-State Circuits Conference Digest Technical Papers, pp. 282–283, Feb 2016
D. Gubbins, B. Lee, P.K. Hanumolu, U. Moon, Continuous-time input pipeline ADC. IEEE J. Solid State Circuits 45(8), 1456–1468 (2010)
D. Yoon, S. Ho, H. Lee, A continuous-time sturdy-MASH ΣΔ modulator in 28nm CMOS. IEEE J. Solid State Circuits 50(12), 2880–2890 (2015)
A. Thomsen, D. Kasha, W. Lee, A five stage chopper stabilized instrumentation amplifier using feedforward compensation, in Symposium on VLSI Circuits Digest Technical Papers, pp. 220–223, 1998
P. DeWit, G. Gielen, Complementary DAC topology for reduced output impedance dependency and improved dynamic performance. Electron. Lett. 48(17), 1039–1041 (2012)
B. Murmann, ADC Performance Survey 1997-2015. [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html
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Shibata, H., Dong, Y., Yang, W., Schreier, R. (2017). Continuous-Time MASH Architectures forWideband DSMs. In: Baschirotto, A., Harpe, P., Makinwa, K. (eds) Wideband Continuous-time ΣΔ ADCs, Automotive Electronics, and Power Management. Springer, Cham. https://doi.org/10.1007/978-3-319-41670-0_6
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DOI: https://doi.org/10.1007/978-3-319-41670-0_6
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