Abstract
In this chapter, we present Tunnel FETs (TFETs) obtained with a FDSOI CMOS process flow featuring High-K Metal Gate, ultrathin body compressively strained Si1-xGex (x from 0 to 30 %) based channels, and Si0.7Ge0.3 Raised SD. In-depth characterizations have been conducted to analyze the device structures (TEM, EELS for atom/layer identification, HAADF STEM GPA for strain) and device electrical performance (C(V), I D (V G ) vs. V DS and temperature, I ON , S w , tunnel extractions…). We investigate the tunneling improvements due to the different technological injection boosters: ultrathin body and gate dielectrics, strain, low band gap source, and low temperature SD anneal. The impact on I D (V G ) curves and thus on ON (and OFF) state current, subthreshold slope is presented and discussed. For the first time, TFETs with large ON current (up to 428 µA/µm) are demonstrated (with >×1,000 I ON gain vs. SOI TFETs, and >×35 I ON gain vs. best published pTFETs). Future paths towards further enhanced TFET devices are also detailed.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Sebaugh, A.C., Shang, Q.: Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE 98, 2095 (2010)
Leonelli, D., Vandooren, A., Rooyackers, R., Verhulst A.S., De Gendt, S., Heyns M.M., Groeseneken, G.: Performance enhancement in multi gate tunneling field effect transistors by scaling the fin-width. Jpn. J. Appl. Phys. 49, 04DC10 (2010)
Krishnamohan, T., Kim, D., Raghunathan, S., Saraswat, K.: Double-gate strained-Ge heterostructure Tunneling FET (TFET) with record high drive currents and <60 mV/dec subthreshold slope. In: IEEE International Electron Devices Meeting, IEDM 2008, pp. 947–950 (2008)
Bhuwalka, K.K., Sedlmaier, S., Ludsteck, A.K., Tolksdorf, C., Schulze, J., Eisele, I.: Vertical tunnel field-effect transistor. IEEE Trans. Electron Devices 51, 279–282 (2004)
Mayer, F., Le Royer, C., Damlencourt J.-F., Romanjek, K., Andrieu, F., Tabone, C., Prévitali, B., Déléonibus S.: (2008). Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible Tunnel FET performance. In: IEEE International Electron Devices Meeting, IEDM 2008, pp. 123–126 (2008)
Kim, S.H., Kam, H., Hu, C., Liu, T.-J.K.: Germanium-source Tunnel Field Effect Transistors with record high ION/IOFF. In: 2008 Symposium on VLSI Technology, pp. 178–179 (2009)
Mookerjea, S., Mohata, D., Krishnan, R., Singh, J., Vallett, A., Ali, A., Mayer, T., Narayanan, V., Schlom, D., Liu, A., Datta, S.: Experimental demonstration of 100 nm channel length In0.53Ga0.47As-based vertical inter-band Tunnel Field Effect Transistors (TFETs) for ultra low-power logic and SRAM applications. In: IEEE International Electron Devices Meeting, IEDM 2008, pp. 949–952 (2009)
Jeon, K., Loh, W.-Y., Patel, P., Kang, C. Y., Oh, J., Bowonder, A., Park, C., Park, C.S., Smith, C., Majhi, P., Tseng, H.-H., Jammy, R., Liu, T.-J.K., Hu, C.: Si tunnel transistors with a novel silicided source and 46 mV/dec swing. In: 2010 Symposium on VLSI Technology, pp. 121–123 (2010)
Choi, W.Y., Park, B.-G., Lee, J.D., Liu, T.-J.K.: Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28, 743–745 (2007)
Kane, E.O.: Theory of tunneling. J. Appl. Phys. 32, 83–91 (1961)
Tomioka, K., Yoshimura, M., Fukui, T.: Steep-slope tunnel field-effect transistors using III–V nanowire/Si heterojunction. In: 2010 Symposium on VLSI Technology, pp. 47–48 (2012)
Villalon, A., Le Royer, C., Cassé, M., Cooper, D., Prévitali, B., Tabone, C., Hartmann, J.-M., Perreau, P., Rivallin, P., Damlencourt, J.-F., Allain, F., Andrieu, F., Weber, O., Faynot, O., Poiroux, T.: Strained Tunnel FETs with record ION: first demonstration of ETSOI TFETs with SiGe channel and RSD. In: 2010 Symposium on VLSI Technology, pp. 49–50 (2010)
Knoll, L., Richter, S., Nichau, A., Trellenkamp, S., Schäfer, A., Bourdelle, K.K., Zhao, Q.T., Mantl, S.: Complementary-Tunnel FET inverters with ultrathin strained Si. EuroSOI conference 2013, pp. 1–2 (2011)
Mohata, D.K., Bijesh, R., Mujumdar, S., Eaton, C., Engel-Herbert, R., Mayer, T., Narayanan, V., Fastenau, J.M., Loubychev, D., Liu, A.K., Datta, S.: Demonstration of MOSFET-like on-current performance in arsenide/antimonide Tunnel FETs with staggered hetero-junctions for 300 mV logic applications. In: IEEE International Electron Devices Meeting, IEDM 2011, pp. 781–784 (2011)
Ionescu, A.M., Riel, H.: Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 329 (2010)
Hutin, L., Le Royer, C., Damlencourt, J.-F., Pouydebasque, A., Xu, C., Tabone, C., Hartmann, J.-M., Carron, V., Grampeix, H., Mazzocchi, V., Truche, R., Weber, O., Batude, P., Garros, X., Clavelier, L., Vinet, M., Faynot, O.: 20 nm gate length trigate pFETs on strained SGOI for high performance CMOS. In: 2010 Symposium on VLSI Technology, pp. 37–38 (2010)
Cheng, K., Khakifirooz, A., Kulkarni, P., Kanakasabapathy, S., Schmitz, S., Reznicek, A., Adam, T., Zhu, Y., Li, J., Faltermeier, J., Furukawa, T., Edge, L.F., Haran, B., Seo, S.C., Jamison, P., Holt, J., Li, X., Loesing, R., Zhu, Z., Johnson, R., Upham, A., Levin, T., Smalley, M., Herman, J., Di, M., Wang, J., Sadana, D., Kozlowski, P., Bu, H., Doris, B., O’Neill, J.: Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain. In: 2010 Symposium on VLSI Technology, pp. 212–213 (2009)
Cooper, D., Le Royer, C., Béché, A., Rouvière, J.-L.: Strain mapping for the silicon-on-insulator generation of semiconductor devices by high-angle annular dark field scanning electron transmission microscopy. Appl. Phys. Lett. 100, 233121 (2012)
Acknowledgments
This work was partly supported by the european “STEEPER” project (no. 257267) and the french MINOS network of excellence. The authors thank also B. Prévitali, P. Perreau, F. Allain, F. Andrieu, O. Weber, O. Faynot and T. Poiroux (from CEA Leti) for contributions in device processing, electrical characterization and mana-gerial support
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2014 Springer International Publishing Switzerland
About this chapter
Cite this chapter
Le Royer, C. et al. (2014). High-Performance Tunnel FETs on Advanced FDSOI Platform. In: Nazarov, A., Balestra, F., Kilchytska, V., Flandre, D. (eds) Functional Nanomaterials and Devices for Electronics, Sensors and Energy Harvesting. Engineering Materials. Springer, Cham. https://doi.org/10.1007/978-3-319-08804-4_4
Download citation
DOI: https://doi.org/10.1007/978-3-319-08804-4_4
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-08803-7
Online ISBN: 978-3-319-08804-4
eBook Packages: Chemistry and Materials ScienceChemistry and Material Science (R0)