Abstract
This chapter describes assertion statements in SVA: assertions, assumptions, restrictions, and coverage statements, and how these statements are checked in simulation and in formal verification. It also provides basic information about assertion simulation algorithms.
Language is a mixture of statement and evocation.— Elizabeth Bowen
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Notes
- 1.
In SVA, there is also expect statement used mostly in testbenches, but we do not describe it in this book.
- 2.
The LRM contains contradictory text that should be resolved in the subsequent revision: In Clause 17.5 it states that initial procedures in checkers can contain immediate assertions, but in Clause 17.2 it does not allow immediate assertions in checker body.
- 3.
This means that the value of the variable must be stored in the deferred assertion report queue with the assertion identification.
- 4.
clk and edge clk behave the same way when clk is of type bit, but they behave differently when the type is logic.
- 5.
One could be tempted to say that the attempts begin at times 15, 35, and 65, but recall that the attempts are synchronized with the rising edge of the clock.
- 6.
chandle is a data type used to represent storage for pointers passed to SystemVerilog from C code.
- 7.
In this section, we limit our discussion to deterministic models; study of nondeterministic models is postponed to Chap. 23.
- 8.
In simulation all traces are, of course, finite. In FV, we can also consider infinite traces. This is discussed in Chap. 21.
- 9.
It is conceivable that simulators could also check that the values of the expression in the dist operator used in an assertion or cover satisfy the specified distributions at the end of simulation.
- 10.
See Chap. 6.
- 11.
We ignore here the fact that assumptions may be used as constraints in random simulation . This feature of assumptions is seldom implemented in commercial simulation tools.
References
IEEE Std. 1800–2009, IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language (2009)
IEEE Std. 1800–2012, IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language (2012)
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© 2015 Springer International Publishing Switzerland
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Cerny, E., Dudani, S., Havlicek, J., Korchemny, D. (2015). Assertion Statements. In: SVA: The Power of Assertions in SystemVerilog. Springer, Cham. https://doi.org/10.1007/978-3-319-07139-8_4
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DOI: https://doi.org/10.1007/978-3-319-07139-8_4
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