Abstract
This chapter describes techniques to maximize the achievable efficiency and power density of fully integrated switched-capacitor (SC) DC-DC converters. Circuit design methods to support multiple topologies (and hence output voltages) are described. These techniques are verified by a proof-of-concept converter prototype implemented in 0.374 mm2 of a 32 nm SOI process. The 32-phase interleaved converter can be configured into three topologies to support output voltages of 0.5–1.2 V from a 2 V input supply, and achieves ~80 % efficiency at an output power density of 0.86 W/mm2.
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Alon, E., Le, HP., Crossley, J., Sanders, S.R. (2014). Fully Integrated Switched-Capacitor DC-DC Conversion. In: Baschirotto, A., Makinwa, K., Harpe, P. (eds) Frequency References, Power Management for SoC, and Smart Wireless Interfaces. Springer, Cham. https://doi.org/10.1007/978-3-319-01080-9_8
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DOI: https://doi.org/10.1007/978-3-319-01080-9_8
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