Abstract
This paper focuses on integrating multiple FPGAs for High-Performance Computing (HPC) applications with a priority on computational capability and reliability. It introduces a reliable inter-FPGA cluster architecture, detailing experimental results of FPGA communication layer performance and hardware management using FreeRTOS on a TMR Microblaze processor. The communication layer features a hardware core for inter-FPGA communication performance, evaluated on a multi-FPGA cluster testbed. Results demonstrate high-speed data transfer and fault tolerance. The hardware manager enhances system flexibility, enabling dynamic task scheduling for hardware accelerators. The paper’s benchmark application is an image-processing pipeline, showing practical applicability with data throughput exceeding 67.4 Gb/s and low latency of 288 ns.
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Acknowledgements
The EuFRATE project is financially supported by the European Space Agency (ESA) in response to the call ESA AO/1-10240/20/UK/ND within the ARTES 4.0 CORE competitiveness generic programme line Component A: Advanced Technology, Activity Reference 5C.416.
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Pertuz, S., Wulf, C., Charaf, N., Kalms, L., Göhringer, D. (2024). A Flexible Mixed-Mesh FPGA Cluster Architecture for High Speed Computing. In: Skliarova, I., Brox Jiménez, P., Véstias, M., Diniz, P.C. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2024. Lecture Notes in Computer Science, vol 14553. Springer, Cham. https://doi.org/10.1007/978-3-031-55673-9_19
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