Abstract
This paper presents the results of our first assessment on the emulation of spiking neural networks (SNNs) on Field Programmable Gated Arrays (FPGAs). Three fundamental modules are designed to obtain a fully functional neural network. First, a module that provides the simulation of a single neuron’s properties, characteristics, and behavior using an accurate but, at the same time, a computationally efficient mathematical model is designed. Second, a communication or transmission system called Address Event Representation (AER) is developed to manage the neural network’s information flow between the neurons. Third, a training algorithm - Spike-Timing Dependent Plasticity (STDP), is designed to provide functionality to the neural network. This modular approach provides the necessary flexibility and scalability for simulating various SNNs and the different numbers of neurons. The modules have been implemented using multiple combinational blocks and flip-flops; The network description is performed using Very High-Speed Integrated Circuit Hardware Description Language (VHDL) in the Xilinx Vivado simulator. The SNN model for digit recognition is implemented and emulated on the Basys3 FPGA development board to demonstrate the accuracy of the model’s operation.
Supported by organization “Dataninja” (Trustworthy AI for Seamless Problem Solving: Next-Generation Intelligence Joins Robust Data Analysis).
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Acknowledgement
This research was supported by the research training group “Dataninja” (Trustworthy AI for Seamless Problem Solving: Next-Generation Intelligence Joins Robust Data Analysis), funded by the German federal state of North Rhine-Westphalia.
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Koravuna, S., Sanaullah, Jungeblut, T., Rückert, U. (2023). Digit Recognition Using Spiking Neural Networks on FPGA. In: Rojas, I., Joya, G., Catala, A. (eds) Advances in Computational Intelligence. IWANN 2023. Lecture Notes in Computer Science, vol 14134. Springer, Cham. https://doi.org/10.1007/978-3-031-43085-5_32
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