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Tri-State Circuits

A Circuit Model that Captures RAM

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Advances in Cryptology – CRYPTO 2023 (CRYPTO 2023)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 14084))

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Abstract

We introduce tri-state circuits (TSCs). TSCs form a natural model of computation that, to our knowledge, has not been considered by theorists. The model captures a surprising combination of simplicity and power. TSCs are simple in that they allow only three wire values (0, 1, and undefined – \(\mathcal {Z}\)) and three types of fan-in two gates; they are powerful in that their statically placed gates fire (execute) eagerly as their inputs become defined, implying orders of execution that depend on input. This behavior is sufficient to efficiently evaluate RAM programs.

We construct a TSC that emulates T steps of any RAM program and that has only \(O(T \cdot \log ^3 T \cdot \log \log T)\) gates. Contrast this with the reduction from RAM to Boolean circuits, where the best approach scans all of memory on each access, incurring quadratic cost.

We connect TSCs with Garbled Circuits (GC). TSCs capture the power of garbling far better than Boolean Circuits, offering a more expressive model of computation that leaves per-gate cost essentially unchanged.

As an important application, we construct authenticated Garbled RAM (GRAM), enabling constant-round maliciously-secure 2PC of RAM programs. Let \(\lambda \) denote the security parameter. We extend authenticated garbling to TSCs; by simply plugging in our TSC-based RAM, we obtain authenticated GRAM running at cost \(O(T \cdot \log ^3 T \cdot \log \log T \cdot \lambda )\), outperforming all prior work, including prior semi-honest GRAM.

We also give semi-honest garbling of TSCs from a one-way function (OWF). This yields OWF-based GRAM at cost \(O(T \cdot \log ^3 T \cdot \log \log T \cdot \lambda )\), outperforming the best prior OWF-based GRAM by more than factor \(\lambda \).

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Notes

  1. 1.

    The RAM model we consider is called the word RAM model [Hag98]; it is a RAM with a fixed word size that incurs unit cost per random access. We state the definition of the in Sect. 3. Throughout this work, by ‘RAM’ we mean ‘word RAM’.

  2. 2.

    While tri-state circuits have not been theoretically explored, tri-state gates are used in practice. We chose our naming based on these real-world gates. A key gate in our model, which we call a buffer, exists as a digital logic element called a tri-state buffer. We show that RAM reduces to a relatively small number of such gates.

  3. 3.

    Tri-state circuits are distinct from ternary logic. Ternary logic has been explored by theorists, even in the context of garbling [LY18, NPS99]. In ternary logic, wires can take three distinct values; however, the circuit executes in a standard topological order. In tri-state circuits, gates execute in a data-dependent order.

  4. 4.

    Of course, full semi-honest GC protocols also use OT, which is not implied by OWFs. It is now traditional to view semi-honest GC as a primitive, independent of any particular protocol [BHR12]. This primitive, called a garbling scheme, can be meaningfully instantiated from OWFs alone.

  5. 5.

    We chose division to denote buffers because buffer semantics produce the ‘undefined’ value \(\mathcal {Z}\) when dividing by 0.

  6. 6.

    We use \(\mathcal {Z}\), pronounced ‘nil,’ to denote ‘no signal’. In digital circuits, the ‘no signal’ value is called high impedance, and is denoted ‘hi-Z’. In GC, \(\mathcal {Z}\) on a wire corresponds to \(E\) holding no key on that wire; see Sect. 7.

  7. 7.

    https://eprint.iacr.org/2023/455.

  8. 8.

    One might wish to consider simpler definitions of runtime acyclicity, such as removing inactive buffers from the circuit, then requiring that the remaining graph is acyclic. Unfortunately, our attempts at such a definition admitted circuit designs for which we cannot prove GC security. Such designs feature cycles which set their own control wires. Our pebbling-game-based definition leads to a natural proof of GC security; it is inspired by pebbling-based techniques from adaptively secure GC [HJO+16].

  9. 9.

    In addition to wires that store data elements, stacks include control logic that tracks element positions. Here, we do not simply replace ANDs by buffers (XORs by joins), but rather translate Boolean control logic into tri-state gates via Theorem 1.

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Acknowledgements

Distribution Statement “A”: (Approved for Public Release, Distribution Unlimited). This research was developed with funding from the Defense Advanced Research Projects Agency (DARPA), supported in part by DARPA under Cooperative Agreement HR0011-20-2-0025, and DARPA Contract No. HR001120C0087, Algorand Centers of Excellence programme managed by Algorand Foundation, NSF grants CNS-2246353, CNS-2246354, CNS-2246355, CNS-2001096 and CCF-2220450, US-Israel BSF grant 2015782, Amazon Faculty Award, Cisco Research Award and Sunday Group. Any views, opinions, findings, conclusions or recommendations contained herein are those of the author(s) and should not be interpreted as necessarily representing the official policies, either expressed or implied, of DARPA, the Department of Defense, the Algorand Foundation, or the U.S. Government. The U.S. Government is authorized to reproduce and distribute reprints for governmental purposes not withstanding any copyright annotation therein.

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Authors and Affiliations

  1. UIUC, Champaign, USA

    David Heath

  2. Georgia Tech, Atlanta, Georgia

    Vladimir Kolesnikov

  3. UCLA, Los Angeles, USA

    Rafail Ostrovsky

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  1. David Heath
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Correspondence to David Heath .

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  1. Rambus Inc., San Jose, CA, USA

    Helena Handschuh

  2. Brown University, Providence, RI, USA

    Anna Lysyanskaya

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Heath, D., Kolesnikov, V., Ostrovsky, R. (2023). Tri-State Circuits. In: Handschuh, H., Lysyanskaya, A. (eds) Advances in Cryptology – CRYPTO 2023. CRYPTO 2023. Lecture Notes in Computer Science, vol 14084. Springer, Cham. https://doi.org/10.1007/978-3-031-38551-3_5

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