Abstract
With the serious scaling limitations of complementary metal-oxide-semiconductor technology, emerging spintronic devices have attracted recent attention for next-generation energy-efficient and secure systems. Voltage-Gated Spin-Orbit Torque (VGSOT) based Magnetic Tunnelling Junction (MTJ) device is proved to show lower energy consumptions with stochastic switching, process variations, and chaotic magnetization. Exploiting these intrinsic variations, this paper for the first time presents a reconfigurable arbiter physically unclonable function (PUF). Further, the PUF functionality is validated considering VGSOT MTJ and 45nm CMOS technology. Considering the state of VGSOT devices, the proposed PUF is observed to be fully reconfigurable. Considering the abilities of VGSOT, PUF shows higher uniqueness of 50.2% at a supply voltage of 0.8V. Additionally, PUF achieves high reliability of 95.8% considering supply voltage and temperature variations. Moreover, at a supply voltage of 0.8V, the proposed PUF achieves lower energy consumption of 24fJ/bit.
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References
Zhang, D., Zeng, L., Zhang, Y., Klein, J.O., Zhao, W.: Reliability enhanced hybrid CMOS/MTJ logic circuit architecture. IEEE Trans. Mag. 53(11), 1–5 (2017)
Bohr, M.T., Young, I.A.: CMOS scaling trends and beyond. IEEE Micro. 37(6), 20–29 (2017)
Zhang, D., et al.: Reliability-enhanced separated pre-charge sensing amplifier for hybrid CMOS/MTJ logic circuits. IEEE Trans. Mag. 53(9), 1–5 (2017)
Chun, K.C., Zhao, H., Harms, J.D., Kim, T.H., Wang, J.P., Kim, C.H.: A scaling roadmap and performance evaluation in in- plane and perpendicular MTJ based STT-MRAMs for high-density cache memory. IEEE J. Solid State Circuits 48(2), 598–610 (2013)
Augustine, C., Mojumder, N., Fong, X., Choday, H., Park, S.P., Roy, K.: STT-MRAMs for future universal memories: Perspective and prospective. In: 28th International Conference on Microelectronics Proceedings, pp. 349–355. IEEE, Nis, Serbia (2012)
Kitagata, D., Sugahara, S.: Design and energy-efficient architectures for nonvolatile static random access memory using magnetic tunnel junctions. Jpn. J. Appl. Phys. 58(SB), SBBB12 (2019)
Ikeda, S., et al.: Perpendicular-anisotropy CoFeB-MgO based magnetic tunnel junctions scaling down to 1X nm. In: IEEE International Electron Devices Meeting, 2014, pp. 33.2.1–33.2.4. IEEE, San Francisco, CA, USA (2014)
Sarkar, M.R., Bappy, M.M.A., Azmir, M.M., Rashid, D.M., Hasan, S.I.: VG-SOT MRAM Design and Performance Analysis. In: IEEE 12th Annual Information Technology, Electronics and Mobile Communication Conference, pp. 715–719. IEEE, Vancouver, BC, Canada (2021)
Zhang, K., Zhang, D., Wang, C., Zeng, L., Wang, Y., Zhao, W.: Compact modeling and analysis of voltage-gated spin-orbit torque magnetic tunnel junction. IEEE Access 8, 50792–50800 (2020)
Wang, C., et al.: Magnetic nonvolatile SRAM based on voltage-gated spin-orbit-torque magnetic tunnel junctions. IEEE Trans. Electron Dev. 67(5), 1965–1971 (2020)
Devadas, S., Suh, E., Paral, S., Sowell, R., Ziola, T., Khandelwal, V.: Design and implementation of PUF-based unclonable RFID ICs for anti-counterfeiting and security applications. In: IEEE International Conference on RFID, pp. 58–64. IEEE, Las Vegas, NV, USA (2008)
Lee, J.W., Lim, D., Gassend, B., Suh, G.E., Van Dijk, M., Devadas, S.: A technique to build a secret key in integrated circuits for identification and authentication applications. In: Symposium on VLSI Circuits. Digest of Technical Papers, pp. 176–179. IEEE, Honolulu, HI, USA (2004)
Suh, G.E., Devadas, S.: Physical unclonable functions for device authentication and secret key generation. In: 44th ACM/IEEE Design Automation Conference, pp. 9–14. IEEE, San Diego, CA, USA (2007)
Wang, Y., Wang, C., Gu, C., Cui, Y., ONeill, M., Liu, W.: Theoretical analysis of delay-based pufs and design strategies for improvement. In: IEEE International Symposium on Circuits and Systems, pp. 1–5. IEEE, Sapporo, Japan (2019)
Garg, A., Kim, T.T.: Design of SRAM PUF with improved uniformity and reliability utilizing device aging effect. In: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1941–1944. IEEE, Melbourne, VIC, Australia (2014)
Sakib, S., Rahman, M.T., Milenković, A., Ray, B.: Flash memory based physical unclonable function. In: 2019 SoutheastCon, pp. 1–6. IEEE, Huntsville, AL, USA (2019)
Sushma, R., Murty, N. S.: Feedback oriented XORed flip-flop based arbiter PUF. In: International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT), pp. 1444–1448. IEEE, Msyuru, India (2018)
Manual of Compact Model of Voltage-Gated SOT, http://www.spinlib.com
Zhao, W., Chappert, C., Javerliac, V., Noziere, J.P.: High speed, high stability and low power sensing amplifier for MTJ/CMOS hybrid logic circuits. IEEE Trans. Mag. 45(10), 3784–3787 (2009)
Japa, A., Mujumdar, M.K., Sahoo, S.K., Vaddi, R.: Tunnel FET-based ultra-lightweight reconfigurable TRNG and PUF design for resource-constrained internet of things. Int. J. Circuit Theory Appl. 49(8), 2299–2311 (2021)
Venkatesh, A., Venkatasubramaniyan, A. B., Xi, X., Sanyal, A.: 0.3 pJ/bit machine learning resistant strong PUF using subthreshold voltage divider array. IEEE Trans. Circuits Syst. II: Express Briefs 67(8), 1394–1398 (2019)
Tanaka, Y., et al.: Physically unclonable functions with voltage-controlled magnetic tunnel junctions. IEEE Trans. Mag. 57(2), 1–6 (2021)
Lim, D., Lee, J. W., Gassend, B., Suh, G. E., Van Dijk, M., Devadas, S.: Extracting secret keys from integrated circuits. IEEE Trans. Very Large Scale Integr. Syst. 13(10), 1200–1205 (2005)
Dodo, S. B., Bishnoi, R., Nair, S. M., Tahoori, M. B.: A Spintronics memory PUF for resilience against cloning counterfeit. IEEE Trans. Very Large Scale Integr. Syst. 27(11), 2511–2522 (2019)
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Das, K.K., Japa, A., Gupta, D. (2022). A Reconfigurable Arbiter PUF Based on VGSOT MTJ. In: Shah, A.P., Dasgupta, S., Darji, A., Tudu, J. (eds) VLSI Design and Test. VDAT 2022. Communications in Computer and Information Science, vol 1687. Springer, Cham. https://doi.org/10.1007/978-3-031-21514-8_27
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