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Completion Detection in Asynchronous Circuits

Toward Solution of Clock-Related Design Challenges

  • Book
  • © 2022

Overview

Authors:
  1. Pallavi Srivastava

    1. Taylor’s University, Subang Jaya, Malaysia

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  • Analyzes circuit design techniques in the context of timing constraints
  • Develops a generic, deterministic completion detection scheme
  • Demonstrates a single-precision, asynchronous bundled data barrel shifter

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Table of contents (7 chapters)

  1. Front Matter

    Pages i-xv
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  2. Introduction to Asynchronous Circuit Design

    • Pallavi Srivastava
    Pages 1-13

  3. Preliminary Considerations for Asynchronous Circuit Design

    • Pallavi Srivastava
    Pages 15-28

  4. Completion Detection Schemes for Asynchronous Design Style

    • Pallavi Srivastava
    Pages 29-44

  5. Case Studies: Barrel Shifter and Binary Adders

    • Pallavi Srivastava
    Pages 45-58

  6. Generic Architecture of Deterministic Completion Detection Scheme

    • Pallavi Srivastava
    Pages 59-68

  7. Architecture Optimisation Using Deterministic Completion Detection

    • Pallavi Srivastava
    Pages 69-89

  8. Simulations

    • Pallavi Srivastava
    Pages 91-108

  9. Back Matter

    Pages 109-119
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Keywords

About this book

This book is intended for designers with experience in traditional (clocked) circuit design, seeking information about asynchronous circuit design, in order to determine if it would be advantageous to adopt asynchronous methodologies in their next design project.  The author introduces a generic approach for implementing a deterministic completion detection scheme for asynchronous bundled data circuits that incorporates a data-dependent computational process, taking advantage of the average-case delay. The author validates the architecture using a barrel shifter, as shifting is the basic operation required by all the processors. The generic architecture proposed in this book for a deterministic completion detection scheme for bundled data circuits will facilitate researchers in considering the asynchronous design style for developing digital circuits.

Authors and Affiliations

  • Taylor’s University, Subang Jaya, Malaysia

    Pallavi Srivastava

About the author

Pallavi Srivastava holds a Ph.D. in Electronics Engineering from Taylor's University, Malaysia (2022). She is an innovative and passionate educator having nine years of experience in industry and academics. She received her Master of Technology in Control Systems from VJTI, Mumbai, India (2012), and Bachelor of Technology in Electronics and Communication Engineering from Uttar Pradesh Technical University, India (2009), both with first-class honors. Her Master's dissertation was focused on designing an observer for Quantum Systems using Contraction Theory which is a recently developed nonlinear control system tool. Her research work also includes the design of fractional order controllers for robotic manipulators. She has authored papers in peer-reviewed journals and international conferences. Currently, Pallavi is working on the asynchronous design of digital circuits and its application. More precisely, she is working towards developing a deterministic completion detection scheme for single-rail asynchronous circuits.


Bibliographic Information

  • Book Title: Completion Detection in Asynchronous Circuits

  • Book Subtitle: Toward Solution of Clock-Related Design Challenges

  • Authors: Pallavi Srivastava

  • DOI: https://doi.org/10.1007/978-3-031-18397-3

  • Publisher: Springer Cham

  • eBook Packages: Computer Science, Computer Science (R0)

  • Copyright Information: The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2022

  • Hardcover ISBN: 978-3-031-18396-6Published: 10 November 2022

  • Softcover ISBN: 978-3-031-18399-7Published: 11 November 2023

  • eBook ISBN: 978-3-031-18397-3Published: 08 November 2022

  • Edition Number: 1

  • Number of Pages: XV, 119

  • Number of Illustrations: 14 b/w illustrations, 51 illustrations in colour

  • Topics: Circuits and Systems, Processor Architectures

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