Skip to main content

Test and Reliability of Approximate Hardware

  • Chapter
  • First Online:
Approximate Computing

Abstract

The undeniable need of energy efficiency in today’s devices is leading to the adoption of innovative computing paradigms—such as Approximate Computing. As this paradigm is gaining increasing interest, important challenges, as well as opportunities, arise concerning the dependability of those systems. This chapter will focus on test and reliability issues related to approximate hardware systems. It will cover problems and solutions concerning the impact of the approximation on hardware defect classification, test generation, and test application. Moreover, the impact of the approximation on the fault tolerance will be discussed, along with related design solutions to mitigate it.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 79.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 99.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 129.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Al-Maaitah K, Qiqieh I, Soltan A, Yakovlev A. Configurable-accuracy approximate adder design with light-weight fast convergence error recovery circuit. In: 2017 IEEE Jordan conference on applied electrical engineering and computing technologies (AEECT). 2017. pp. 1–6. https://doi.org/10.1109/AEECT.2017.8257753.

  2. Anghel L, Benabdenbi M, Bosio A, Traiola M, Vatajelu EI. Test and reliability in approximate computing. J Electron Test. 2018;34(4):375–87. https://doi.org/10.1007/s10836-018-5734-9.

    Article  Google Scholar 

  3. Avirneni NDP, Somani A. Low overhead soft error mitigation techniques for high-performance and aggressive designs. IEEE Trans Comput. 2012;61(4):488–501. https://doi.org/10.1109/TC.2011.31

    Article  MathSciNet  Google Scholar 

  4. Avizienis A, Laprie JC, Randell B. Fundamental concepts of dependability. 2001. http://www.cs.ncl.ac.uk/publications/trs/papers/739.pdf.

  5. Benedetto J, Eaton P, Avery K, Mavis D, Gadlage M, Turflinger T, Dodd P, Vizkelethyd G. Heavy ion-induced digital single-event transients in deep submicron processes. IEEE Trans Nuclear Sci. 2004;51(6):3480–85. https://doi.org/10.1109/TNS.2004.839173.

    Article  Google Scholar 

  6. Borade S, Nakiboǧlu B, Zheng L. Unequal error protection: An information-theoretic perspective. IEEE Trans Inf Theory. 2009;55(12):5511–39. https://doi.org/10.1109/TIT.2009.2032819

    Article  MathSciNet  Google Scholar 

  7. Bosio A, O’Connor I, Traiola M, Echavarria J, Teich J, Hanif MA, Shafique M, Hamdioui S, Deveautour B, Girard P, Virazel A, Bertels K. Emerging computing devices: Challenges and opportunities for test and reliability*. In: 2021 IEEE European test symposium (ETS). 2021. pp. 1–10. https://doi.org/10.1109/ETS50041.2021.9465409.

  8. Bottoni C, Coeffic B, Daveau JM, Naviner L, Roche P. Partial triplication of a SPARC-V8 microprocessor using fault injection. In: 2015 IEEE 6th Latin American symposium on circuits systems (LASCAS). 2015. pp. 1–4. https://doi.org/10.1109/LASCAS.2015.7250415

  9. Bushnell M, Agrawal, V.: Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits. 2000. https://doi.org/10.1007/b117406

  10. Castano V, Schagaev I. Resilient computer system design. Cham: Springer International Publishing; 2015. https://link.springer.com/book/10.1007/978-3-319-15069-7. OCLC: 1194524751.

  11. Chandrasekharan A, Eggersglüß S, Große D, Drechsler R. Approximation-aware testing for approximate circuits. In: 2018 23rd Asia and South Pacific design automation conference (ASP-DAC). 2018. pp. 239–244. https://doi.org/10.1109/ASPDAC.2018.8297312.

  12. Chen CC, Milor L. Microprocessor aging analysis and reliability modeling due to back-end wearout mechanisms. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2015;23(10):2065–76. https://doi.org/10.1109/TVLSI.2014.2357756.

    Article  Google Scholar 

  13. Deveautour B, Traiola M, Virazel A, Girard P. QAMR: an approximation-based fully reliable TMR alternative for area overhead reduction. In: 2020 IEEE European test symposium (ETS). 2020. pp. 1–6. https://doi.org/10.1109/ETS48528.2020.9131574.

  14. Deveautour B, Virazel A, Girard P, Gherman V. On using approximate computing to build an error detection scheme for arithmetic circuits. J Electron Test. 2020;36(1):33–46. https://doi.org/10.1007/s10836-020-05858-5. http://link.springer.com/10.1007/s10836-020-05858-5.

  15. Dodd P, Shaneyfelt M, Felix J, Schwank J. Production and propagation of single-event transients in high-speed digital logic ICs. IEEE Trans Nuclear Sci. 2004;51(6):3278–84. https://doi.org/10.1109/TNS.2004.839172.

    Article  Google Scholar 

  16. Dubrova E. Fault-tolerant design. New York: Springer; 2013. https://doi.org/10.1007/978-1-4614-2113-9. http://link.springer.com/10.1007/978-1-4614-2113-9.

  17. Dutta A, Jas A. Combinational logic circuit protection using customized error detecting and correcting codes. In: 9th international symposium on quality electronic design (ISQED 2008). 2008. pp. 68–73. https://doi.org/10.1109/ISQED.2008.4479700. ISSN: 1948-3295.

  18. Eldred RD. Test routines based on symbolic logical statements. J. ACM. 1959;6(1):33–37. https://doi.org/10.1145/320954.320957

    Article  MathSciNet  Google Scholar 

  19. Ernst D, Kim NS, Das S, Pant S, Rao R, Pham T, Ziesler C, Blaauw D, Austin T, Flautner K, Mudge T. Razor: a low-power pipeline based on circuit-level timing speculation. In: Proceedings. 36th annual IEEE/ACM international symposium on microarchitecture, 2003. MICRO-36. 2003. pp. 7–18. https://doi.org/10.1109/MICRO.2003.1253179.

  20. Fazeli M, Miremadi S, Ejlali A, Patooghy A. Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies. IET Comput Digit Techniques. 2009;3(3):289. https://doi.org/10.1049/iet-cdt.2008.0099. https://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2008.0099.

  21. Fazeli M, Ahmadian SN, Miremadi SG, Asadi H, Tahoori MB. Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs). In: 2011 design, automation test in Europe. 2011. pp. 1–6. https://doi.org/10.1109/DATE.2011.5763020. ISSN: 1558-1101.

  22. Ferlet-Cavrois V, Massengill LW, Gouker P. Single event transients in digital CMOS—a review. IEEE Trans Nuclear Sci. 2013;60(3):1767–90. https://doi.org/10.1109/TNS.2013.2255624.

    Article  Google Scholar 

  23. Frohwerk RA. Signature analysis: a new digital field service method. Hewlett-Packard Journal. 1977;28(9):2–8.

    Google Scholar 

  24. Fujiwara H. FAN: A fanout-oriented test pattern generation algorithm. In: The IEEE international symposium on circuits and systems (ISCAS). 1985. https://www.researchgate.net/publication/234044505_FAN_A_fanout-oriented_test_pattern_generation_algorithm.

  25. Gebregiorgis A, Tahoori MB. Test pattern generation for approximate circuits based on Boolean satisfiability. In: 2019 Design, automation test in Europe conference exhibition (DATE). 2019. pp. 1028–1033. https://doi.org/10.23919/DATE.2019.8714898.

  26. Gielen G, Wit PD, Maricau E, Loeckx J, Martin-Martinez J, Kaczer B, Groeseneken G, Rodriguez R, Nafria M. Emerging yield and reliability challenges in nanometer CMOS technologies. In: Design, Automation and Test in Europe (DATE). 2008. pp. 1322–1327. https://doi.org/10.1109/DATE.2008.4484862.

  27. Göessel M, Ocheretny V, Sogomonyan E, Marienfeld D. New methods of concurrent checking, frontiers in electronic testing, vol. 42. Dordrecht: Springer Netherlands; 2008. https://doi.org/10.1007/978-1-4020-8420-1. http://link.springer.com/10.1007/978-1-4020-8420-1.

  28. Gomes IA, Martins MG, Reis AI, Kastensmidt FL. Exploring the use of approximate TMR to mask transient faults in logic with low area overhead. Microelectron Reliab. 2015;55(9):2072–2076. https://doi.org/10.1016/j.microrel.2015.06.125. https://www.sciencedirect.com/science/article/pii/S0026271415300676. Proceedings of the 26th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis.

  29. Gomes IAC, Martins M, Reis A, Kastensmidt FL. Using only redundant modules with approximate logic to reduce drastically area overhead in TMR. In: 2015 16th Latin-American test symposium (LATS). 2015. pp. 1–6. https://doi.org/10.1109/LATW.2015.7102522.

  30. Hamdioui S. Electronics and computing in nano-era: The good, the bad and the challenging. In: 2015 10th international conference on design technology of integrated systems in nanoscale era (DTIS). 2015. pp. 1–1. https://doi.org/10.1109/DTIS.2015.7127342

  31. Hareland S, Maiz J, Alavi M, Mistry K, Walsta S, Dai C. Impact of CMOS process scaling and SOI on the soft error rates of logic processes. In: 2001 Symposium on VLSI technology. Digest of technical papers (IEEE Cat. No.01 CH37184). 2001. pp. 73–74. https://doi.org/10.1109/VLSIT.2001.934953.

  32. Heimerdinger W, Weinstock C. A conceptual framework for system fault tolerance. Tech. Rep. CMU/SEI-92-TR-033, Software Engineering Institute, Carnegie Mellon University, Pittsburgh, PA. 1992. http://resources.sei.cmu.edu/library/asset-view.cfm?AssetID=11747.

  33. Huang W, Stan MR, Gurumurthi S, Ribando RJ, Skadron K. Interaction of scaling trends in processor architecture and cooling. In: 2010 26th Annual IEEE semiconductor thermal measurement and management symposium (SEMI-THERM). 2010. pp. 198–204. https://doi.org/10.1109/STHERM.2010.5444290.

  34. International Roadmap for Devices and Systems (IRDSTM) 2020 Edition - IEEE IRDSTM. https://irds.ieee.org/editions/2020.

  35. Kahng AB, Kang S. Accuracy-configurable adder for approximate arithmetic designs. In: DAC design automation conference 2012. 2012. pp. 820–5. https://doi.org/10.1145/2228360.2228509.

  36. Koren I, Krishna CM. Fault-tolerant systems. San Francisco (CA): Morgan Kaufmann; 2021. https://doi.org/10.1016/C2018-0-02160-X. www.sciencedirect.com/book/9780128181058/fault-tolerant-systems.

  37. Kumar R. Temperature adaptive and variation tolerant CMOS circuits. Madison: University of Wisconsin; 2008.

    Google Scholar 

  38. Liang J, Han J, Lombardi F. New metrics for the reliability of approximate and probabilistic adders. IEEE Trans Comput. 2013;62(9):1760–71. https://doi.org/10.1109/TC.2012.146

    Article  MathSciNet  Google Scholar 

  39. Lienig, J, Bruemmer, H.: Reliability Analysis. In: Fundamentals of Electronic Systems Design, pp. 45–73. Springer International Publishing, Cham (2017). https://doi.org/10.1007/978-3-319-55840-0_4. http://link.springer.com/10.1007/978-3-319-55840-0_4.

  40. Lyons RE, Vanderkulk W. The use of triple-modular redundancy to improve computer reliability. IBM J Res Devel. 1962;6(2):200–9. https://doi.org/10.1147/rd.62.0200.

    Article  Google Scholar 

  41. Maheshwari A, Burleson W, Tessier R. Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2004;12(3):299–311. https://doi.org/10.1109/TVLSI.2004.824302. http://ieeexplore.ieee.org/document/1281801/

  42. Maniatakos M, Makris Y. Workload-driven selective hardening of control state elements in modern microprocessors. In: 2010 28th VLSI test symposium (VTS). 2010. pp. 159–64. https://doi.org/10.1109/VTS.2010.5469589. ISSN: 2375-1053.

  43. Mathew J, Shafik RA, Pradhan DK, editors. Energy-efficient fault-tolerant systems. New York: Springer; 2014. https://doi.org/10.1007/978-1-4614-4193-9. http://link.springer.com/10.1007/978-1-4614-4193-9.

  44. Mehrara M, Attariyan M, Shyam S, Constantinides K, Bertacco V, Austin T. Low-cost protection for SER upsets and silicon defects. In: 2007 Design, automation test in Europe conference exhibition. 2007. pp. 1–6. https://doi.org/10.1109/DATE.2007.364449.

  45. Mittal S. A survey of techniques for approximate computing. ACM Comput Surv. 2016;48(4):62:1–62:33. https://doi.org/10.1145/2893356.

  46. Mohanram K, Touba N. Cost-effective approach for reducing soft error failure rate in logic circuits. In: International test conference, 2003. Proceedings. ITC 2003. vol. 1. 2003. pp. 893–901. https://doi.org/10.1109/TEST.2003.1271075. ISSN: 1089-3539.

  47. Mrazek V, Hrbacek R, Vasicek Z, Sekanina L. EvoApprox8b: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. In: Design, automation test in Europe conference exhibition (DATE). 2017. pp. 258–61. https://doi.org/10.23919/DATE.2017.7926993.

  48. Naeimi H, DeHon A. Fault-tolerant sub-lithographic design with rollback recovery. Nanotechnology. 2008;19(11):115708. https://doi.org/10.1088/0957-4484/19/11/115708. https://iopscience.iop.org/article/10.1088/0957-4484/19/11/115708.

  49. NanGate: Nangate 45nm open cell library. http://www.nangate.com/?pageid=2325.

  50. Neumann Jv. Probabilistic logics and the synthesis of reliable organisms from unreliable components. In: Shannon CE, McCarthy J, editors. Automata studies. (AM-34). 1956. pp. 43–98. Princeton University Press. https://doi.org/10.1515/9781400882618-003. https://www.degruyter.com/document/doi/10.1515/9781400882618-003/html.

  51. Oda S, Ferry DK, editors. Nanoscale silicon devices, 0 edn. CRC Press; 2018. https://doi.org/10.1201/b19251. https://www.taylorfrancis.com/books/9781482228687.

  52. Pagliarini SN, Naviner LAdB, Naviner JF. Selective hardening methodology for combinational logic. In: 2012 13th Latin American test workshop (LATW). 2012. pp. 1–6. https://doi.org/10.1109/LATW.2012.6261262. ISSN: 2373-0862.

  53. Peterson WW, Weldon EJ. Error-correcting codes, 2nd ed. Cambridge: MIT Press; 1972.

    MATH  Google Scholar 

  54. Polian I, Reddy SM, Becker B. Scalable calculation of logical masking effects for selective hardening against soft errors. In: 2008 IEEE Computer Society annual symposium on VLSI. 2008. pp. 257–262. https://doi.org/10.1109/ISVLSI.2008.22. ISSN: 2159-3477.

  55. Rehman S, Prabakaran BS, El-Harouni W, Shafique M, Henkel J. Heterogeneous approximate multipliers: architectures and design methodologies. 2019. pp. 45–66. Springer. https://doi.org/10.1007/978-3-319-99322-5_3.

  56. Rushby J. Formal methods and their role in the certification of critical systems. In: Shaw R, editor. Safety and reliability of software based systems. London: Springer; 1997. pp. 1–42.

    Google Scholar 

  57. Sachdev M. Defect oriented testing for CMOS analog and digital circuits, Frontiers in electronic testing. vol. 10. Boston: Springer US; 1999. https://doi.org/10.1007/978-1-4757-4926-7. http://link.springer.com/10.1007/978-1-4757-4926-7.

  58. Sánchez-Clemente A, Entrena L, García-Valderas M, López-Ongil C. Logic masking for set mitigation using approximate logic circuits. In: 2012 IEEE 18th international on-line testing symposium (IOLTS). 2012. pp. 176–181. https://doi.org/10.1109/IOLTS.2012.6313868.

  59. Sanchez-Clemente AJ, Entrena L, Hrbacek R, Sekanina L. Error mitigation using approximate logic circuits: A comparison of probabilistic and evolutionary approaches. IEEE Trans Reliab. 2016;65(4):1871–83. https://doi.org/10.1109/TR.2016.2604918.

    Article  Google Scholar 

  60. Santoro M. New methodologies for eliminating no trouble found, no fault found and other non repeatable failures in depot settings. In: 2008 IEEE AUTOTESTCON. 2008. pp. 336–40. https://doi.org/10.1109/AUTEST.2008.4662636. ISSN: 1558-4550.

  61. Segura J, Hawkins CF. CMOS electronics: how it works, how it fails. New York: IEEE Press/Wiley-Interscience; 2004. OCLC: ocm53192483.

    Google Scholar 

  62. Shafique M, Ahmad W, Hafiz R, Henkel J. A low latency generic accuracy configurable adder. In: 2015 52nd ACM/EDAC/IEEE design automation conference (DAC). 2015. pp. 1–6. https://doi.org/10.1145/2744769.2744778.

  63. Shivakumar P. Techniques to improve the hard and soft error reliability of distributed architectures. Thesis. 2007. https://repositories.lib.utexas.edu/handle/2152/3304.

  64. Sierawski BD, Bhuva BL, Massengill LW. Reducing soft error rate in logic circuits through approximate logic functions. IEEE Trans Nuclear Sci. 2006;53(6):3417–21. https://doi.org/10.1109/TNS.2006.884352.

    Article  Google Scholar 

  65. Sosnowski J. Transient fault tolerance in digital systems. IEEE Micro. 1994;14(1):24–35. https://doi.org/10.1109/40.259897. http://ieeexplore.ieee.org/document/259897/.

  66. Srinivasan J, Adve S, Bose P, Rivers J. The case for lifetime reliability-aware microprocessors. In: Proceedings. 31st Annual international symposium on computer architecture. 2004. pp. 276–287. https://doi.org/10.1109/ISCA.2004.1310781.

  67. Srinivasan J, Adve S, Bose P, Rivers J. The impact of technology scaling on lifetime reliability. In: International conference on dependable systems and networks. 2004. pp. 177–186. https://doi.org/10.1109/DSN.2004.1311888.

  68. Subramanian V, Somani AK. Conjoined pipeline: Enhancing hardware reliability and performance through organized pipeline redundancy. In: 2008 14th IEEE Pacific Rim international symposium on dependable computing. 2008. pp. 9–16. https://doi.org/10.1109/PRDC.2008.54.

  69. Traiola M. Test techniques for approximate digital circuits. PhD thesis, Université Montpellier. 2019. https://tel.archives-ouvertes.fr/tel-02485781.

  70. Traiola M, Virazel A, Girard P, Barbareschi M, Bosio A. Investigation of mean-error metrics for testing approximate integrated circuits. In: 2018 IEEE international symposium on defect and fault tolerance in VLSI and nanotechnology systems (DFT). 2018. pp. 1–6. https://doi.org/10.1109/DFT.2018.8602939.

  71. Traiola M, Virazel A, Girard P, Barbareschi M, Bosio A. On the comparison of different ATPG approaches for approximate integrated circuits. In: IEEE 21st international symposium on design and diagnostics of electronic circuits systems. 2018. pp. 85–90. https://doi.org/10.1109/DDECS.2018.00022.

  72. Traiola M, Virazel A, Girard P, Barbareschi M, Bosio A. Testing approximate digital circuits: Challenges and opportunities. In: 2018 IEEE 19th Latin-American test symposium (LATS). 2018. pp. 1–6. https://doi.org/10.1109/LATW.2018.8349681.

  73. Traiola M, Virazel A, Girard P, Barbareschi M, Bosio A. A test pattern generation technique for approximate circuits based on an ILP-formulated pattern selection procedure. IEEE Trans Nanotechnol. 2019. p. 1. https://doi.org/10.1109/TNANO.2019.2923040.

  74. Traiola M, Virazel A, Girard P, Barbareschi M, Bosio A. Maximizing yield for approximate integrated circuits. In: 2020 design, automation test in Europe conference exhibition (DATE). 2020.

    Google Scholar 

  75. Traiola M, Virazel A, Girard P, Barbareschi M, Bosio A. A survey of testing techniques for approximate integrated circuits. Proc IEEE. 2020;108(12):2178–94. https://doi.org/10.1109/JPROC.2020.2999613.

    Article  Google Scholar 

  76. Tran D, Virazel A, Bosio A, Dilillo L, Girard P, Pravossoudovitch S, Wunderlich HJ. A hybrid fault tolerant architecture for robustness improvement of digital circuits. In: 2011 Asian test symposium. 2011. pp. 136–141. https://doi.org/10.1109/ATS.2011.89. ISSN: 2377-5386.

  77. Wali I. Circuit and system fault tolerance techniques. PhD thesis, Université Montpellier. 2016. https://tel.archives-ouvertes.fr/tel-01807927.

  78. Wali I, Deveautour B, Virazel A, Bosio A, Girard P, Sonza Reorda M. A low-cost reliability vs. cost trade-off methodology to selectively harden logic circuits. J Electron Test. 2017;33(1):25–36. https://doi.org/10.1007/s10836-017-5640-6. https://doi.org/10.1007/s10836-017-5640-6.

  79. Wali I, Traiola M, Virazel A, Girard P, Barbareschi M, Bosio A. Towards approximation during test of integrated circuits. In: 2017 IEEE 20th international symposium on design and diagnostics of electronic circuits systems (DDECS). 2017. pp. 28–33. https://doi.org/10.1109/DDECS.2017.7934574.

  80. Wali I, Virazel A, Bosio A, Dilillo L, Girard P. An effective hybrid fault-tolerant architecture for pipelined cores. In: 2015 20th IEEE European test symposium (ETS). 2015. pp. 1–6. https://doi.org/10.1109/ETS.2015.7138733.

  81. Weide-Zaage K, Chrzanowska-Jeske M. Semiconductor devices in harsh conditions. https://www.routledge.com/Semiconductor-Devices-in-Harsh-Conditions/Weide-Zaage-Chrzanowska-Jeske/p/book/9780367656362.

  82. Wirnshofer M. Variation-aware adaptive voltage scaling for digital CMOS circuits. Springer series in advanced microelectronics. Springer Netherlands; 2013. https://doi.org/10.1007/978-94-007-6196-4. https://www.springer.com/gp/book/9789400761957.

  83. Yang S. Logic synthesis and optimization benchmarks user guide version 3.0; 1991. https://doi.org/10.1.1.49.591.

  84. Yao J, Okada S, Masuda M, Kobayashi K, Nakashima Y. DARA: A low-cost reliable architecture based on unhardened devices and its case study of radiation stress test. IEEE Trans Nuclear Sci. 2012;59(6):2852–8. https://doi.org/10.1109/TNS.2012.2223715.

    Article  Google Scholar 

  85. Yazdanbakhsh A, Mahajan D, Esmaeilzadeh H, Lotfi-Kamran P. AxBench: A multiplatform benchmark suite for approximate computing. IEEE Des Test. 2017;34(2):60–8. https://doi.org/10.1109/MDAT.2016.2630270.

    Article  Google Scholar 

  86. Ye R, Wang T, Yuan F, Kumar R, Xu Q. On reconfiguration-oriented approximate adder design and its application. In: 2013 IEEE/ACM international conference on computer-aided design (ICCAD). 2013. pp. 48–54. https://doi.org/10.1109/ICCAD.2013.6691096.

  87. Zhou Q, Mohanram K. Gate sizing to radiation harden combinational logic. IEEE Trans Comput Aided Des Integr Circ Syst. 2006;25(1):155–66. https://doi.org/10.1109/TCAD.2005.853696.

    Article  Google Scholar 

  88. Zhu N, Goh WL, Yeo KS. An enhanced low-power high-speed adder for error-tolerant application. In: Proceedings of the 2009 12th international symposium on integrated circuits. 2009. pp. 69–72.

    Google Scholar 

  89. Zoellin CG, Wunderlich HJ, Polian I, Becker B. Selective hardening in early design steps. In: 2008 13th European test symposium. 2008. pp. 185–190. https://doi.org/10.1109/ETS.2008.30. ISSN: 1558-1780.

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Patrick Girard .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2022 The Author(s), under exclusive license to Springer Nature Switzerland AG

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Traiola, M., Deveautour, B., Bosio, A., Girard, P., Virazel, A. (2022). Test and Reliability of Approximate Hardware. In: Liu, W., Lombardi, F. (eds) Approximate Computing. Springer, Cham. https://doi.org/10.1007/978-3-030-98347-5_10

Download citation

  • DOI: https://doi.org/10.1007/978-3-030-98347-5_10

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-98346-8

  • Online ISBN: 978-3-030-98347-5

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics