Abstract
Modern FPGAs are equipped with the possibility of Partial Reconfiguration (PR) which along with other benefits can be used to enhance the security of cryptographic implementations. This feature requires development of alternative designs to be exchanged during run-time. In this work, we propose dynamically alterable circuits by exploring netlist randomization which can be utilized with PR as a countermeasure against physical attacks, in particular side-channel attacks. The proposed approach involves modification of an AES implementation at the netlist level in order to create circuit variants which are functionally identical but structurally different. In preliminary experiments, power traces of these variants have been shuffled to replicate the effect of partial reconfiguration. With these dynamic circuits, our experimental results show an increase in the resistance against power side-channel attacks by a factor of \({\sim }12.6\) on a Xilinx ZYNQ UltraScale+ device.
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Acknowledgement
This work has been supported by the German Federal Ministry for Eduction and Research (BMBF) within the collaborative research project “SecRec” (16KIS0609).
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Asghar, A., Hettwer, B., Karimov, E., Ziener, D. (2021). Increasing Side-Channel Resistance by Netlist Randomization and FPGA-Based Reconfiguration. In: Derrien, S., Hannig, F., Diniz, P.C., Chillet, D. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2021. Lecture Notes in Computer Science(), vol 12700. Springer, Cham. https://doi.org/10.1007/978-3-030-79025-7_12
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