Abstract
Vector computing can be read as equipping a processing unit with replicated ALUs. To benefit from this hardware concurrency, we have to phrase our calculations as operation sequences over small vectors. We discuss what well-suited loops that can exploit vector units have to look like, we discuss the relation between loops with vectorisation and partial loop unrolling, and we discuss the difference between horizontal and vertical vectorisation. These insights allow us to study realisation flavours of vectorisation on the chip: Are wide vector registers used, or do we introduce hardware threads with lockstepping, how do masking and blending facilitate slight thread divergence, and why does non-continuous data access require us to gather and scatter register content?
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Notes
- 1.
In return, vendors sell you a temporary increase of the clock speed as turbo boost; which sounds nice but actually means that you will not benefit from this with a floating-point heavy code.
- 2.
Two different things are called CUDA: There is a programming language (a C dialect) that we call CUDA, and there is a hardware architecture paradigm called CUDA. We do not discuss the CUDA programming here.
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Weinzierl, T. (2021). SIMD Vector Crunching. In: Principles of Parallel Scientific Computing. Undergraduate Topics in Computer Science. Springer, Cham. https://doi.org/10.1007/978-3-030-76194-3_7
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DOI: https://doi.org/10.1007/978-3-030-76194-3_7
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