Abstract
In the process of logic synthesis, the method of representing Boolean functions has great importance. The development of synthesis methods is inseparably connected with the search for new forms of description.
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References
Akers SB (1978) Binary decision diagrams. IEEE Trans Comput C-27(6):509–516
Bryant R (1986) Graph based algorithms for boolean function manipulation. IEEE Trans Comput C-35(8):677–691
Kubica M, Kania D, Kulisz J (2019) A technology mapping of FSMs based on a graph of excitations and outputs. IEEE Access 7:16123–16131
Micheli G (1994) Synthesis and optimization of digital circuits. McGraw-Hill, New York
Ashar P, Devades S, Newton A (1992) Sequential logic synthesis. Kluwer Academic Publishers, Berlin
Brayton R, Hachtel G, McMullen C, Sangiovanni-Vincentelli A (1984) Logic minimization algorithms for VLSI synthesis. Kluwer Academic Publishers, Berlin
Espresso (1993) A source code. http://embedded.eecs.berkeley.edu/pubs/downloads/espresso/index.htm
Rudell R (1986) Multiple-valued logic minimization for PLA synthesis, Memorandum No. UCB/ERL M86-65 (Berkeley). (http://www.eecs.berkeley.edu/Pubs/TechRpts/1986/ERL-86-65.pdf
EspFormat. http://www.ecs.umass.edu/ece/labs/vlsicad/ece667/links/espresso.5.html
Czerwiński R, Kania D (2013) Finite state machine logic synthesis for CPLDs, Springer, Lecture Notes in Electrical Engineering, vol 231, XVI, 2013, 172 p
Bolton M (1990) Digital systems design with programmable logic. Addison-Wesley Publishing Company, Boston
Karnaugh M (1953) The map method for synthesis of combinational logic circuits. Trans Am Instit Electr Eng Part I: Commun Electr 72(5):593–599
Kania D (2012) Układy logiki programowalne – Podstawy syntezy i sposoby odwzorowania technologicznego, Wydawnictwo Naukowe PWN, Warszawa
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Kubica, M., Opara, A., Kania, D. (2021). Methods for Representing Boolean Functions—Basic Definitions. In: Technology Mapping for LUT-Based FPGA. Lecture Notes in Electrical Engineering, vol 713. Springer, Cham. https://doi.org/10.1007/978-3-030-60488-2_2
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DOI: https://doi.org/10.1007/978-3-030-60488-2_2
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