Abstract
This book developed and presented a new methodology that allows including a MC simulations-based circuit yield estimation in an analog IC sizing and optimization loop. The new developed methodology was added as a new feature to the state-of-the-art AIDA-C sizing and optimization tool and has been proved by the test cases presented. This chapter presents the conclusion of this work, and future research directions for continuing the development of new features for the AIDA framework.
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Canelas, A.M.L., Guilherme, J.M.C., Horta, N.C.G. (2020). Conclusion and Future Work. In: Yield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies. Springer, Cham. https://doi.org/10.1007/978-3-030-41536-5_7
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DOI: https://doi.org/10.1007/978-3-030-41536-5_7
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