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High DC-Gain Two-Stage OTA Using Positive Feedback and Split-Length Transistor Techniques

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Advances in Data Science, Cyber Security and IT Applications (ICC 2019)

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Abstract

A fully differential and split-length transistors (SLT) CMOS two-stage operational transconductance amplifier (OTA) is presented. The proposed amplifier is designed in a CMOS 65 nm process with a 1.2 V supply voltage. The main advantage of this proposed amplifier is the use of both positive feedback technique and the split-length transistors to enhance its DC-gain without affecting the stability, unity-gain bandwidth (UGBW), output voltage swing and power dissipation of the conventional two-stage amplifier. The DC-gain is increased by about 40 dB. The two-stage OTA has been successfully verified and a comprehensive analysis has been provided for common mode gain, differential-mode gain, power supply rejection ratio, input-referred noise and the effect of using SLT on DC-gain sensitivity. The proposed two-stage OTA is used in a flip-around sample-and-hold amplifier (SHA) circuit. A total harmonic distortion of about 0.0018% is obtained for the output spectrum of the SHA circuit.

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References

  1. Zhao, X., Fang, H., Ling, T., et al.: Low-voltage process-insensitive frequency compensation method for two-stage OTA with enhanced DC gain. AEU-Int. J. Electron. Commun. 69, 685–690 (2015)

    Article  Google Scholar 

  2. Neag, M., Oneţ, N., Kovács, I., et al.: Comparative analysis of simulation based methods for deriving the phase- and gain-margins of feedback circuits with op-amps. IEEE Trans. Circ. Syst. II. Exp. Briefs 62, 625–634 (2015)

    MathSciNet  Google Scholar 

  3. Zuo, L., Islam, S.K.: Low-voltage bulk-driven operational amplifier with improved transconductance. IEEE Trans. Circ. Syst. I. Regul. Pap. 60, 2084–2091 (2013)

    Article  Google Scholar 

  4. Esparza-Alfaro, F., Pennisi, S., Palumbo, G., et al.: Low-power class-AB CMOS voltage feedback current operational amplifier with tunable gain and bandwidth. IEEE Trans. Circ. Syst. II. Exp. Briefs 61, 574–578 (2014)

    Google Scholar 

  5. Cho, Y.K., Park, B.H.: Single op-amp second-order loop filter for continuous-time delta–sigma modulators. Electron. Lett. 51, 619–621 (2015)

    Article  Google Scholar 

  6. He, L., Zhu, G., Long, F., et al.: A multibit delta–sigma modulator with double noise-shaped segmentation. IEEE Trans. Circ. Syst. II. Exp. Briefs 62, 241–245 (2015)

    Google Scholar 

  7. Sahoo, B.D., Inamdar, A.: Thermal-noise-canceling switched-capacitor circuit. IEEE Trans. Circ. Syst. II. Exp. Briefs 63, 628–632 (2016)

    Google Scholar 

  8. Johns, D., Martin, K.: Analog Integrated Circuit Design. Wiley, Hoboken (1997)

    MATH  Google Scholar 

  9. Asloni, M., Hadidi, K., Khoei, A.: Design of a new folded cascode Op-Amp using positive feedback and bulk amplification. IEICE Trans. Electron. 90, 1253–1257 (2007)

    Article  Google Scholar 

  10. Gulati, K., Lee, H.S.: A high-swing CMOS telescopic operational amplifier. IEEE J. Solid-State Circ. 33, 2010–2019 (1998)

    Article  Google Scholar 

  11. Bult, K., Geelen, G.J.G.M.: A fast-settling CMOS op-amp for SC circuits with 90-dB DC gain. IEEE J. Solid-State Circ. 25, 1379–1384 (1990)

    Article  Google Scholar 

  12. Kulej, T., Khateb, F.: Bulk-driven adaptively biased OTA in 0.18 μm CMOS. Electron Lett. 51, 458–460 (2015)

    Article  Google Scholar 

  13. Raikos, G., Vlassis, S.: Low-voltage bulk-driven input stage with improved transconductance. Int. J. Circ. Theory Appl. 39, 327–339 (2011)

    Article  Google Scholar 

  14. Ferreira, L.H.C., Sonkusale, S.R.: A 60-dB gain OTA operating at 0.25-V power supply in 130-nm digital CMOS process. IEEE Trans. Circ. Syst. I. Regul. Pap. 61, 1609–1617 (2014)

    Article  Google Scholar 

  15. Razavi, B.: Design of Analog CMOS Integrated Circuits. McGraw-Hill, New York (2001)

    Google Scholar 

  16. Akbari, M., Hashemipour, O.: Enhancing transconductance of ultra-lowpower two-stage folded cascode OTA. Electron. Lett. 50, 1514–1516 (2014)

    Article  Google Scholar 

  17. Khameh, H., Shamsi, H.: On the design of a low-voltage twostage OTA using bulk-driven and positive feedback techniques. Int. J. Electron. 99, 1309–1315 (2012)

    Article  Google Scholar 

  18. Khameh, H., Mirzaie, H., Shamsi, H.: A new two-stage op-amp using hybrid cascode compensation, bulk-driven, and positive feedback techniques. In: 8th IEEE International NEWCAS Conference on (NEWCAS), pp. 109–112 (2010)

    Google Scholar 

  19. Pude, M., Mukund, P.R., Burleson, J.: Positive feedback for gain enhancement in sub-100 nm multi-GHz CMOS amplifier design. Int. J. Circ. Theory Appl. 43, 111–124 (2013)

    Article  Google Scholar 

  20. Tran, P.T., Hess, H.L., Noren, K.V., et al.: Gain-enhancement differential amplifier using positive feedback. In: IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 718–721 (2012)

    Google Scholar 

  21. Farahmand, S., Shamsi, H.: Positive feedback technique for DC-gain enhancement of folded cascode op-amps. In: IEEE 10th International New Circuits and Systems Conference (NEWCAS), pp. 261–264 (2012)

    Google Scholar 

  22. Yavari, M.: Hybrid cascode compensation for two-stage CMOS op-amps. IEICE Trans. Electron. 88, 1161–1165 (2005)

    Article  Google Scholar 

  23. Cunha, A.I.A., Schneider, M.C., Galup-Montoro, C.: An MOS transistor model for analog circuit design. IEEE J. Solid-State Circ. 33, 1510–1519 (1998)

    Article  Google Scholar 

  24. Ferreira, L.H.C., Pimenta, T.C.: Extraction of MOS parameters from BSIM3v3 model using minimum square method for quick manual design. Proc. IEE Circ. Dev. Syst. 153, 153–158 (2006)

    Article  Google Scholar 

  25. Ferreira, L.H.C., Pimenta, T.C., Moreno, R.L.: An ultra-low-voltage ultralow-power CMOS miller OTA with rail-to-rail input/output swing. IEEE Trans. Circ. Syst. II. Exp. Briefs 54, 843–847 (2007)

    Article  Google Scholar 

  26. Ning, N., Yang, F., Zhiling, S., et al.: A low-sensitivity negative resistance load fully differential OTA under low voltage 40 nm CMOS logic process. Chin. Sci. Pap. 688, 1–7 (2012)

    Google Scholar 

  27. Saxena, V., Baker, R.J.: Indirect compensation techniques for three-stage fully-differential op-amps. 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 588–591 (2010)

    Google Scholar 

  28. Furth, P.M., Thota, N.R., Nammi, V.H., et al.: Low dropout (LDO) voltage regulator design using split-length compensation. In: IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1088–1091 (2012)

    Google Scholar 

  29. Assaad, R.S., Silva-Martinez, J.: Enhancing general performance of folded cascode amplifier by recycling current. Electron. Lett. 43, 1–2 (2007)

    Article  Google Scholar 

  30. Gray, P.R., Meyer, R.G.: Analysis and Design of Analog İntegrated Circuits. Wiley, Hoboken (2001)

    Google Scholar 

  31. Ho, K.P., Chan, C.F., Choy, C.S., et al.: Reversed nested Miller compensation with voltage buffer and nulling resistor. IEEE J. Solid-State Circ. 38, 1735–1738 (2003)

    Article  Google Scholar 

  32. Grasso, A.D., Palumbo, G., Pennisi, S.: Advances in reversed nested miller compensation. IEEE Trans. Circ. Syst. I. Regul. Pap. 54, 1459–1470 (2007)

    Article  Google Scholar 

  33. Grasso, A.D., Palumbo, G., Pennisi, S.: Three-stage CMOS OTA for large capacitive loads with efficient frequency compensation scheme. IEEE Trans. Circ. Syst. II. Exp. Briefs 53, 1044–1048 (2006)

    Article  Google Scholar 

  34. Anisheh, S.M., Shamsi, H., Mirhassani, M.: Positive feedback technique and split-length transistors for DC-gain enhancement of two-stage op-amp. IET Circ. Dev. Syst. 11, 605–612 (2017)

    Article  Google Scholar 

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Acknowledgements

This project was supported by the Deanship of Scientific Research at Prince Sattam Bin Abdulaziz University under the research project 2019/01/11709. It was conducted jointly in cooperation with Aix-Marseille University, IM2NP laboratory UMR-CNRS 7334, France, during the academic year 2018-2019.

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Correspondence to Jamel Nebhen .

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Nebhen, J., Masmoudi, M., Rahajandraibe, W., Aguir, K. (2019). High DC-Gain Two-Stage OTA Using Positive Feedback and Split-Length Transistor Techniques. In: Alfaries, A., Mengash, H., Yasar, A., Shakshuki, E. (eds) Advances in Data Science, Cyber Security and IT Applications. ICC 2019. Communications in Computer and Information Science, vol 1098. Springer, Cham. https://doi.org/10.1007/978-3-030-36368-0_24

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  • DOI: https://doi.org/10.1007/978-3-030-36368-0_24

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-36367-3

  • Online ISBN: 978-3-030-36368-0

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