Abstract
A balanced method for the minimization of incompletely specified finite state machines (FSMs) implemented on Field Programmable Logic Devices (FPGA) is proposed. In this method, such optimization criteria as the power consumption, speed of operation and device area are taken into account already at the stage of minimizing internal states. The method also takes into consideration the technological features of programmable logic and the state encoding method. The method is based on sequential merging of two internal states. For this purpose, the set of all pairs of states that can be merged is found, and the pair of states that has the highest rank is chosen for merging. The rank is calculated on the base of estimations of power, speed and area parameters and the user is able to choose the direction of minimization by setting weights for each criteria. In addition, the proposed method allows to minimize the number of transitions and redundant input variables of the FSM. Algorithms for the estimation of optimization criteria values are described and experimental results are also discussed.
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The research was done in the framework of the grant S/WI/3/2018 and financed from the funds for science by MNiSW.
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Klimowicz, A. (2019). Balanced Power, Speed and Area Minimization of Finite State Machines for FPGA Devices. In: Saeed, K., Chaki, R., Janev, V. (eds) Computer Information Systems and Industrial Management. CISIM 2019. Lecture Notes in Computer Science(), vol 11703. Springer, Cham. https://doi.org/10.1007/978-3-030-28957-7_39
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