FPGA Implementation of Rate Compatible Non-binary LDPC Codes

Abstract

In order to solve the problem of the requirements of communication on UAN, an improved construction of Rate-compatible Low-Density Parity-Codes (RC-LDPC) based on progress edge growth (PEG) is proposed. The algorithm uses high bit rate to low bit rate compatible with the way to achieve multi-rate, after constructing the master code with high bit rate, we continue to use an improved PEG algorithm to increase the decoding performance of the master code by increasing the large ring in the matrix. The simulation shows that this code covered multi-rates, and the performance of this code is better than other traditional LDPC codes with single rate. For this code, based on exclusive OR (XOR) gate array and random access memory (RAM) combined with the coding architecture, reduce the encoder for the on-chip resource occupancy, to achieve multi-code rate multi-code length switch. The encoder was implemented on the chip of Cyclone IV with Verilog HDL language. The reports show that the encoder reduce the application of the cyclic shift memory and the occupancy of the chip resource at the same time.