Abstract
SystemVerilog enables modeling at a higher level of abstraction through the use of 2-state data types, enumerated types, and user-defined types. These are complemented by new specialized always procedural blocks, always_comb, always_ff and always_latch. These and other new modeling constructs have been discussed in the previous chapters of this book.
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© 2004 Springer Science+Business Media Dordrecht
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Sutherland, S., Davidmann, S., Flake, P. (2004). Modeling Finite State Machines with SystemVerilog. In: SystemVerilog For Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-6682-0_7
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DOI: https://doi.org/10.1007/978-1-4757-6682-0_7
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-6684-4
Online ISBN: 978-1-4757-6682-0
eBook Packages: Springer Book Archive