Abstract
Transistor gate patterning is the primary application of a high-resolution lithographic system in the semiconductor industry. The gate itself is typically a long, narrow line of polysilicon whose width (known as the transistor gate “length”) determines the device switching speed. The uniformity of the gate is critical for device electrical performance and yield. Gate patterning is performed after significant device processing. Therefore the feature must be accurately aligned to the previously patterned regions. It must also be written over the sample topography created by the prior fabrication steps.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
K. F. Lee, R. H. Yan, D. Y. Jeon, G. M. Chin, Y. O Kim, D. M. Tennant, B. Razavi, H. D. Lin, Y. G. Wey, E. H. Westerwick, M. D. Morris, R. W. Johnson, T. M. Liu, M. Tarsia, M. Cerullo, R. G. Swartz, and A. Ourmazd, “Room temperature 0.1 µm CMOS technology with 11.8 ps gate delay,” Proc. IEDM, 131–134 (1993).
Y. Taur, S. Wind, Y. J. Mii, Y. Lii, D. Moy, K. A. Jenkins, C. L. Chen, P. J. Coane, D. Klaus, J. Bucchignano, M. Rosenfield, M. G. R. Thomson, and M. Polcari, “High performance 0.1 µm CMOS devices with 1.5 V power supply,” Proc. IEDM, 127–130 (1993).
T. Hori, “A 0.1 µm CMOS technology with tilt-implanted punchthrough stopper,” Proc. IEDM, 75–78 (1994).
B. Davari, “CMOS technology scaling, 0.1 µm and beyond,” Proc. IEDM, 555558 (1996).
S. C. Minne, H. T. Soh, P. Flueckiger, and C. F. Quate, “Fabrication of 0.1 µm metal oxide semiconductor field-effect transistors with the atomic force microscope,” Appl. Phys. Lett. 66, 703–705 (1995).
E. Kooi, The Invention of LOCOS (New York: The Institute of Electrical and Electronics Engineers, Inc., 1991 ).
S. Wolf, Silicon Processing for the VLSI Era (Sunset Beach, California: Lattice Press, 1990 ).
International Technology Roadmap for Semiconductors (San Jose: Semiconductor Industry Association, 1997). Data also reflects 1998 update to the roadmap.
W. H. Arnold, B. Singh, and K. Phan, “Line width metrology requirement for sub-micron lithography,” Solid State Technol. 32, 139–145 (1989).
L. Bauch, U. Jagdhold, and M. Bottcher, “Electron beam lithography over topography,” Microelectron. Eng. 30, 53–56 (1996).
T. Waas, E. Eisenmann, O. Vollinger, and H. Hartmann, “Proximity correction for high CD accuracy and process tolerance,” Microelectron. Eng. 27, 179–182 (1995).
J. M. Pimbley and J. D. Meindl, “MOSFET scaling limits determined by subthreshold conduction,” Trans. Elec. Dev. 36, 1711–1721 (1989).
R. R. Troutman, “VLSI limitations from drain-induced barrier lowering,” IEEE J. of Solid-State Circuits SC-14, 383–391 (1979).
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2001 Springer Science+Business Media New York
About this chapter
Cite this chapter
Soh, H.T., Guarini, K.W., Quate, C.F. (2001). Critical Dimension Patterning Using SPL. In: Scanning Probe Lithography. Microsystems, vol 7. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3331-0_5
Download citation
DOI: https://doi.org/10.1007/978-1-4757-3331-0_5
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-4894-6
Online ISBN: 978-1-4757-3331-0
eBook Packages: Springer Book Archive