Abstract
Extraction is a very common concept in ECAD, which is generally used as a means of validation, such as parameter extraction or netlist extraction from mask layout. In this chapter we present an extraction technique intended to provide the necessary link between hardware-oriented processor models and advanced code generation algorithms Instruction-set extraction reads an HDL processor model and emits the set of valid instructions for the specified processor. The organization of this chapter is as follows. First, we analyze different processor description styles and we define the necessary terminology. The main part of this chapter is constituted by algorithms for extracting the instruction set from an HDL processor model. The overall extraction process consists of three main phases: construction of an internal processor model, behavioral analysis of single modules, and structural analysis for composing local module operations to global instruction patterns.
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© 1997 Springer Science+Business Media Dordrecht
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Leupers, R. (1997). Instruction-Set Extraction. In: Retargetable Code Generation for Digital Signal Processors. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2570-4_3
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DOI: https://doi.org/10.1007/978-1-4757-2570-4_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5181-6
Online ISBN: 978-1-4757-2570-4
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