Skip to main content

Manufacture of an Integrated Circuit Package

  • Chapter
Shape Memory Effects in Alloys

Abstract

Many techniques have been used to produce integrated circuit packages. All of these assembly methods, such as beam lead, spider, flip chip and others require a large number of separate and distinct processing steps, frequently causing high costs and poor reliability (1). In the chip and wire process, for example, a large number of very fine aluminum lead wires are bonded by ultrasonic cold welding to pads on the semiconductor chip, and in turn to tips of leads on the metal lead frame. Failure of the devise will occur if any of these bonds are defective.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Similar content being viewed by others

References

  1. J. M. Salzer, Insulation/Circuits, 29, February (1975).

    Google Scholar 

  2. S. H. Butt, “Developments in Copper Alloys for Semiconductor Packages”, Technical Report No. W71–12.1, paper presented at 1971 Westec Conference.

    Google Scholar 

  3. R. F. Otte, Patent No. 3, 588, 618, (1971).

    Google Scholar 

  4. H. Pops, Trans., AIME 236, 1532, (1966).

    Google Scholar 

  5. H. Pops, Met. Trans., 1, 251, (1970).

    Google Scholar 

  6. A. Cabo and H. Pops, unpublished results, report to Essex International, Inc., (1971).

    Google Scholar 

  7. R. J. Wasilewski, Met. Trans., 2, 2973, (1971).

    Article  CAS  Google Scholar 

  8. J. Perkins, Met. Trans., 4, 2709, (1973).

    Article  CAS  Google Scholar 

  9. H. Pops and B. Johnson, Patent No. 3, 854, 200, (1974).

    Google Scholar 

  10. R. D. Garwood, Special Report 93, The Iron and Steel Institute, Scarborough Conference, 90, (1965).

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 1975 Springer Science+Business Media New York

About this chapter

Cite this chapter

Pops, H. (1975). Manufacture of an Integrated Circuit Package. In: Perkins, J. (eds) Shape Memory Effects in Alloys. Springer, Boston, MA. https://doi.org/10.1007/978-1-4684-2211-5_29

Download citation

  • DOI: https://doi.org/10.1007/978-1-4684-2211-5_29

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4684-2213-9

  • Online ISBN: 978-1-4684-2211-5

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics