Abstract
This chapter presents Low-Power (LP) design methodologies at several abstraction levels such as physical, logical, architectural, and algorithmic levels. All the power reduction techniques discussed are related to the dynamic power dissipation. It is shown that LP techniques, at the high-level (algorithmic and architectural) of the design, lead to power savings of several orders of magnitude. Many examples are included to give the reader a quantitative picture of LP issues. Several LP techniques, particularly at the circuit level, have already been discussed in Chapters 4, 6, and 7 including those related to static power considerations. However, they are not reconsidered in this chapter. The power estimation techniques at the circuit, logical, architectural and behavioral levels are overviewed. Power analysis at high-level allows an early prediction and optimization of the power of a system. The LP concepts such as switching activity, glitching, etc., discussed in Chapter 4 are used throughout this chapter.
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Bellaouar, A., Elmasry, M.I. (1995). Low-Power VLSI Design Methodology. In: Low-Power Digital VLSI Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2355-0_8
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DOI: https://doi.org/10.1007/978-1-4615-2355-0_8
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