Complexity Issues

Abstract

As discussed earlier, many synthesis tools for LUT architectures have been proposed -XNFMAP [105], chortle [35], chortle-crf [36], mis-fpga [78, 79], HYDRA [33], Xmap [50], VISMAP [104], ASYL [97], flow-map [24] to name a few. We can compare one tool with another and get an idea of the relative quality of these tools, but there is no way of judging the absolute quality of the solutions generated by any of these tools. This is an important concern, as it is directly related to the research effort that should go into improving these tools and the solution quality. One way to answer this question is to compute the minimum number of LUTs needed for the realization of a Boolean function. However, as shown in Corollary 2.3.2, this is a difficult problem - in fact, NP-hard. In fact, even the problem of technology mapping for minimum LUTs is NP-hard. It is desirable then to at least derive tight lower and upper bounds; with tight bounds one can evaluate with some confidence how far various synthesis tools are from optimality. Also, if good upper bounds can be obtained, one can use them to predict quickly the LUT-count of a circuit without technology mapping.