Abstract
In hardware, combinational logic outputs reflect the values of the inputs to that block of logic. There is no storage in combinational logic, so each time any input changes, the output may be affected. To properly model the behavior of combinational logic using a Verilog always procedure requires using an @(<list_of_signals>) construct at the very beginning of the procedure. The list of signals must include every input to that block of combinational logic. An input to the logic is any signal whose value may be read by that procedure. Two examples of a simple block of combinational logic modeled using a Verilog always procedure are:
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© 2002 Springer Science+Business Media New York
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Sutherland, S. (2002). Combinational logic sensitivity lists. In: Verilog — 2001. The Springer International Series in Engineering and Computer Science, vol 652. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-1713-9_13
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DOI: https://doi.org/10.1007/978-1-4615-1713-9_13
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-5691-2
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