Abstract
The simplest form of a network is composed of a single link with one sender and one receiver. In parallel to the data wires, the sender and the receiver need to exchange some extra information that will allow them to develop a common understanding on the intentions of each side. Figure 2.1 a shows a sender and a receiver that besides the data wires drive two extra wires, a ready and a valid bit, that are responsible for co-ordinating the flow of data from one side to the other.
(a) A flow-controlled channel with ready/valid handshake and (b) an example of transferring of three words between the sender and the receiver
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
This is not needed in the case that two flow-controlled buffers communicate directly without any intermediate pipeline registers.
- 2.
The internal latency imposed by the sender and receiver can be included in L f and L b respectively.
References
Arvind (2013) Fifos and ehrs: Designing modules with concurrent methods. In: Lecture Notes MIT course 6.375: Complex Digital Systems
Bertozzi D, Benini L (2004) Xpipes: A Network-on-Chip Architecture for Gigascale Systems-on-Chip. IEEE Circuits and Systems Magazine 4
Butts M, Jones AM, Wasson P (2007) A structural object programming model, architecture, chip and tools for reconfigurable computing. In: Field-Programmable Custom Computing Machines, 2007. FCCM 2007. 15th Annual IEEE Symposium on, pp 55–64
Concer N, Petracca M, Carloni L (2008) Distributed flit-buffer flow control for networks-on-chip. In: Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS ’08, pp 215–220
Cortadella J, Kishinevsky M, Grundmann B (2006) Synthesis of Synchronous Elastic Architectures. In: Proc. ACM/IEEE Design Automation Conference, pp 657–662
Dally WJ, Seitz CL (1986) The torus routing chip. Journal of Parallel and Distributed Computing 1(3):187–196
Dally WJ, Towles B (2004) Principles and Practices of Interconnection Networks. Morgan Kaufmann
Ginosar R (2011) Metastability and synchronizers: A tutorial. IEEE Design & Test of Computers 28(5):23–35
Kermani P, Kleinrock L (1979) Virtual cut-through: a new computer communication switching technique. Computer Networks 3(4):276–286
Kung NT, Morris R (1995) Credit-based flow control for atm networks. Network, IEEE 9(2):40–48
Michelogiannakis G, Dally W (2013) Elastic buffer flow control for on-chip networks. IEEE Trans on Computers 62(2)
Minkenberg C, Gusat M (2009) Design and performance of speculative flow control for high-radix datacenter interconnect switches. Journal of Parallel and Distributed Computing 69(8):680–695
Moscibroda T, Mutlu O (2009) A case for bufferless routing in on-chip networks. In: Proceedings of the 36th International Symposium on Computer Architectur, IEEE
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2015 Springer Science+Business Media New York
About this chapter
Cite this chapter
Dimitrakopoulos, G., Psarras, A., Seitanidis, I. (2015). Link-Level Flow Control and Buffering. In: Microarchitecture of Network-on-Chip Routers. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4301-8_2
Download citation
DOI: https://doi.org/10.1007/978-1-4614-4301-8_2
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4614-4300-1
Online ISBN: 978-1-4614-4301-8
eBook Packages: EngineeringEngineering (R0)