Abstract
Information decoding and security using minimal hardware and software resources is very indispensable in mission and safety critical applications. Currently, various methodologies have been proposed in which hardware exhibits parallelism either implicitly or explicitly. In this chapter, we report an enhancement in DLX processor instruction set for efficient implementation of Viterbi decoding algorithm and enhanced AES encryption algorithm. We also present results for enhanced AES encryption algorithm for PicoJava II processor. We create a custom permutation instruction (WUHPERM) and a custom trellis expansion instruction (Texpand) in CPUSIM simulator on RISC-based architecture. In addition, we implement the same WUHPERM instruction on Mic-1 simulator which is based on JVM microarchitecture. The results show substantial improvements in the execution speed of approximately six times when the WUHPERM instruction is implemented in RISC architecture and eight times for stack-based architecture. The execution time is stupendously improved to approximately three times when Texpand instruction is implemented for RISC architecture.
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Ahmed, W., Mahmood, H., Siddique, U. (2013). Efficient Implementation of Computationally Complex Algorithms: Custom Instruction Approach. In: Ao, SI., Gelman, L. (eds) Electrical Engineering and Intelligent Systems. Lecture Notes in Electrical Engineering, vol 130. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-2317-1_4
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DOI: https://doi.org/10.1007/978-1-4614-2317-1_4
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