Abstract
This chapter describes how fault tolerance can be achieved by means of coding. Coding is a powerful technique which helps us avoid unwanted information changes during data storage or transmission. Code selection for a given application is usually guided by the types and rate of errors required to be tolerated, their consequences, and the overhead associated with implementing encoding and decoding. In this section, we consider many important families of codes, including parity codes. linear codes, cyclic codes, unordered codes, and arithmetic codes.
“If you make a mistake and do not correct it, this is called a mistake.” Confucius.
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References
Anderson, D., Shanley, T.: Pentium Processor System Architecture, 2nd edn. Addison-Wesley, Reading (1995)
Avižienis, A.: Arithmetic error codes: cost and effectiveness studies for application in digital system design. IEEE Trans. Comput. 20(11), 1322–1331 (1971)
Berger, J.M.: A note on an error detection code for asymmetric channels. Inform. Contr. 4, 68–73 (1961)
Berlekamp, E.R.: Nonbinary BCH decoding. In: International Symposium on Information Theory, San Remo, Italy (1967)
Bryant, V.: Metric Spaces: Iteration and Application. Cambridge University Press, Cambridge (1985)
De Micheli, G., Brayton, R., Sangiovanni-Vincentelli, A.: Optimal state assignment for finite state machines. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 4(3), 269–285 (1985)
Dubrova, E.: Multiple-valued logic in VLSI: Challenges and opportunities. In: Proceedings of NORCHIP’99, pp. 340–350 (1999)
Dubrova, E., Mansouri, S.: A BDD-based approach to constructing LFSRs for parallel CRC encoding. In: Proceedings of International Symposium on Multiple-Valued Logic, pp. 128–133 (2012)
Golomb, S.: Shift Register Sequences. Aegean Park Press, Laguna Hills (1982)
Hamming, R.: Error detecting and error correcting codes. Bell Syst. Tech. J. 26(2), 147–160 (1950)
Immink, K.: Reed-Solomon codes and the compact disc. In: S. Wicker, V. Bhargava (eds.) Reed-Solomon Codes and Their Applications, pp. 41–59. Wiley, New York (1999)
Intel Corporation: Embedded Pentium processor family developer’s manual (1998) http://download.intel.com/design/intarch/manuals/27320401.pdf
Jha, N., Wang, S.J.: Design and synthesis of self-checking VLSI circuits. IEEE Trans. Comput. Aided Des. 12, 878–887 (1993)
Johnson, B.W.: The Design and Analysis of Fault Tolerant Digital Systems. Addison-Wesley, Reading (1989)
Lala, P.: Self-Checking and Fault-Tolerant Digital Design. Morgan Kauffmann Publishers, Waltham (2001)
Lavagno, L., Nowick, S.: Asynchronous control circuits. In: S. Hassoun, T. Sasao (eds.) Logic Synthesis and Verification, Lecture Notes in Computer Science, pp. 255–284. Kluwer Academic Publishers, Boston (2002)
Lidl, R., Niederreiter, H.: Introduction to Finite Fields and their Applications. Cambridge University Press, Cambridge (1994)
Mitra, S., McCluskey, E.J.: Which concurrent error detection scheme to choose? In: Proceedings of the 2000 IEEE International Test Conference, pp. 985–994 (2000)
Murray, B.: Journey into space. NASA Historical Reference Collection, pp. 173–175 (1985)
Peterson, W., Brown, D.: Cyclic codes for error detection. Proc. IRE 49(1), 228–235 (1961)
Peterson, W.W., Weldon, E.J.: Error-Correcting Codes, 2nd edn. MIT Press, London (1972)
Pierce, J.: Optical channels: practical limits with photon counting. IEEE Trans. Commun. 26(12), 1819–1821 (1978)
Reed, I.S., Solomon, G.: Polynomial codes over certain finite fields. J. Soc. Ind. Appl. Math. 8(2), 300–304 (1960)
Sayers, I., Kinniment, D.: Low-cost residue codes and their application to self-checking vlsi systems. IEE Proc. Comput. Digit. Tech. 132(4), 197–202 (1985)
Shannon, C.E.: A mathematical theory of communication. Bell Syst. Tech. J. 27, 379–423 (1948)
Smith, D.H., Hughes, L.A., Perkins, S.: A new table of constant weight codes of length greater than 28. Electron. J. Comb. 13, A2 (2006)
Stavinov, E.: A practical parallel CRC generation method. Feature Article, pp. 38–45 (2010)
Strang, G.: Introduction to Linear Algebra, 4th edn. Wellesley-Cambridge Press, Wellesley (2009)
Tang, D.T., Woo, L.S.: Exhaustive test pattern generation with constant weight vectors. IEEE Trans. Comput. C-32, 1145–1150 (1983)
Tezzaron Semiconductor: Soft errors in electronic memory (2004). http://www.tezzaron.com/about/papers/papers.htm
United States Federal Standard 1037C: Telecommunications: Glossary of telecommunication terms. General Services Administration (1996)
United States Postal Service: Domestic mail manual 708.4 - special standards, technical specifications, barcoding standards for letters and flats (2010). http://pe.usps.com/cpim/ftp/manuals/dmm300/708.pdf
Wells, R.B.: Applied Coding and Information Theory for Engineers. Prentice-Hall, Englewood Cliffs (1998)
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Dubrova, E. (2013). Information Redundancy. In: Fault-Tolerant Design. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-2113-9_5
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DOI: https://doi.org/10.1007/978-1-4614-2113-9_5
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