Abstract
THE RECEPTION OF WIRELESS COMMUNICATION STANDARDS, such as WiMAX or WLAN, together with those intended for cellular communication in the same multi-mode chipset is usually considered the main achievement in the evolution towards 4G transceivers [Bran05]. If additional wireless standards, such as low-rate low-distance standards (ZigBee or Bluetooth), positioning systems (GPS) or digital television (DVB-H), are included, the functionality of these types of devices will be boosted.
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Notes
- 1.
Note that these requirements also depend on the resolution of the embedded quantizers and the values of the in-loop coefficients.
- 2.
Consider the case in which, for instance, a two-stage opamp is needed rather than a single-stage one because of the opamp output swing requirements.
- 3.
This reconfiguration strategy is not used in this SDM but in that presented in Chap. 6.
- 4.
The SDM presented in Chap. 6 uses this approach. More details on these kinds of analog adders can be found there. By contrast, the SDM in Fig. 5.1 employs passive adders for power saving.
- 5.
Note that some of these parameters—such as OSR, V ref or B i —can be considered closer to the electrical implementation than to the architecture itself. However, their values will influence the performance of the overall modulator and could be reconfigured as well.
- 6.
Of course, the integrator coefficients (c i ) and the feed-forward coefficients (a j ) are related as described in (3.8) for every stage of the block diagram in Fig. 5.1. This will be addressed later.
- 7.
Section 4.2.1 illustrates that the systemic power loss of the in-band quantization error in the SDM presented in Chap. 4 was 6 dB.
- 8.
High values of d lead to either very low values of c 3 and c 4 or large output swings for the last-stage opamps.
- 9.
The DAC operation is already performed at the sampling capacitors of the front-end integrator controlled by digital signals A i , B i and C i for each stage i. Note that the digital gates that generate these control signals are grouped together in the DAC block in Fig. 5.4; though, formally this block should be denoted as DAC control-signal generator.
- 10.
This voltage is also the input of the embedded quantizer directly connected to the analog adder. Therefore, this voltage is compared with the quantizer voltage tabs.
- 11.
Note that these parasitic capacitances account not only for the parasitics of the sampling capacitors but also for the parasitic capacitances of the associated switches.
- 12.
Scaling refers here to the reduction of the capacitor value for minimum opamp loads up to the point at which thermal noise and mismatching start playing an important role.
- 13.
The thermal noise power extracted from this procedure, is later included in the modulator electrical model in SPECTRE via an input source. The data provided to this source is taken from a MATLAB routine that generates a temporal white-noise sequence for the corresponding noise PSD.
- 14.
The switches on-resistances slow down the dynamic operation of the opamps [Rio06].
- 15.
In order to keep a perfect common-centroid structure for the first analog adder, the unit element of C a 1 that is farthest from C in 1 in the same row should have been placed at the location of C in1, and C in1 at the gravity center of the structure. However the approach in Fig. 5.16 is recommended because C a 1 is made up of 8 elements and C in1 of only 1, and placing C in1 at the actual structural center will entail an increase of the structure and, thus, in the area as well. Therefore, C in1 is placed as close as possible to the gravity center of the structure, while C a 1 only has 1 out of 8 elements that is not correctly placed for a common-centroid distribution.
- 16.
This value corresponds to the input parasitic capacitances of the DAC digital gates driven by the quantizer outputs.
- 17.
The placement of the modulator last stage close to the clock phase generation helps to reduce the influence of the switching noise coupling on the SDM performance. This will be addressed in Sect. 5.4.
- 18.
A p filter is employed for the common-mode voltage distribution on the PCB when this strategy is applied.
- 19.
- 20.
It is well known that the dynamic power of a digital gate is proportional to \(f \cdot C \cdot V_{DDD}^2\) [Sedr82], where f, C and V DDD stand for the operation frequency, the load capacitance and the digital supply voltage, respectively.
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Morgado, A., del Río, R., de la Rosa, J.M. (2011). A 1.2-V 90-nm CMOS Reconfigurable 2-2 Cascade SC ΣΔM for GSM/BT/GPS/UMTS/DVB-H/WiMAX. In: Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-0037-0_5
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