Power Delivery Network Design for 3D IC

Abstract

In this chapter, we first study the impact of P/G TSVs on the power supply noise as well as 3D IC layouts. We perform sign-off static IR-drop analysis on GDSII layouts of 2D and 3D IC designs using commercial-grade tools. We also explore the impact of 3D P/G network topology on IR-drop by varying P/G TSV pitch. Next, we study a non-regular P/G TSV placement algorithm to further reduce the number of P/G TSVs used, while satisfying the given IR-drop noise requirement. Compared with the conventional regular structure, our non-regular P/G TSV placement algorithm reduces the P/G TSV count, wirelength, and footprint area by 59.3, 3.4, and 3.5 % on average, respectively. Next, we study the TSV RC variation impact on 3D power delivery network (PDN). First, we model TSV RC variation due to process variation. Then, we perform sign-off power supply noise analysis of 3D PDN in GDSII layouts which contain power/ground (P/G) TSV RC variation model. We explore the effect of TSV RC variation range, the number of variation sources (P/G TSV count), the number of C4 bumps, and TSV size on the robustness of PDN under TSV RC variation. Our results show that TSV RC variations cause negligible influence on 3D PDN due to much smaller parasitic values of TSVs compared with that of entire PDN.

The materials presented in this chapter are based on [5, 6].