Abstract
In this chapter, we study two methods used in 3D IC placement that effectively exploit the die-to-die thermal coupling in the stack. First, TSVs are spread on each die to reduce the local power density and vertically aligned across dies simultaneously to increase thermal conductivity to the heatsink. Second, we move high-power logic cells to the location that has higher conductivity to the heatsink while moving TSVs in the upper dies so that high-power cells are vertically overlapping below the TSVs. These methods are employed in a force-directed 3D placement successfully and outperform several state-of-the-art placers published in recent literature.
The materials presented in this chapter are based on [1].
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Notes
- 1.
We attempted combining these two methods, but the results were not consistent.
- 2.
This task is challenging due to the discrepancy among the settings and assumptions made in each work. However, we made our best effort to provide fair and meaningful comparison, including in-depth discussions with the authors.
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Lim, S.K. (2013). Thermal-Aware Gate-Level Placement for 3D IC. In: Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9542-1_11
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DOI: https://doi.org/10.1007/978-1-4419-9542-1_11
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