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Case Study

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Multiprocessor Systems on Chip

Abstract

A case study proving feasibility is always key when proposing new design tools and methodologies. It can also clarify the advantages but also limitations of the proposed design methodology.

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Notes

  1. 1.

    Please note that for the coarse-grained annotations, the objective is the hand-optimized assembly code that has been determined to execute more than one order of magnitude faster than the general purpose C code [60]. Clearly this demands the optimized software as a reference implementation, otherwise the estimations would be far off reality ( ∼ 8–10 times).

  2. 2.

    Please note that this result is only valid for the given scenario. In general, the point-to-point communication architecture should be able to achieve superior performance.

References

  1. ARM. AMBA System Architecture. http://www.arm.com/, Jan. 2011.

  2. IBM CoreConnect bus cores. http://www.ibm.com/, Jan. 2011.

  3. S.W. Smith. The Scientist and Engineer’s Guide to Digital Signal Processing. California Technical Publishing, San Diego, CA, USA, 1997.

    Google Scholar 

  4. T. Kempf, E.M. Witte, V. Ramakrishnan, G. Ascheid, M. Adrat, and M. Antweiler. A practical view of SDR baseband processing portability. In Software Defined Radio Technical Conference (SDR’08), Washington, USA, Oct. 2008.

    Google Scholar 

  5. Synopsys DesignWare IP. http://www.synopsys.com, Jan. 2011.

  6. ARM Ltd. ARM Embedded Processors. http://www.arm.com/, Jan. 2011.

  7. K. Karuri, M.A. Al Faruque, S. Kraemer, R. Leupers, G. Ascheid, and H. Meyr. Fine-grained application source code profiling for ASIP design. In 42nd Design Automation Conference, Anaheim, California, USA, June 2005.

    Google Scholar 

  8. C. Lattner and V. Adve. LLVM: A compilation framework for lifelong program analysis and transformation. In Proceedings of the 2004 International Symposium on Code Generation and Optimization (CGO’04), Palo Alto, California, March 2004.

    Google Scholar 

  9. T. Kogel, M. Doerper, T. Kempf, A. Wieferink, R. Leupers, and H. Meyr. Virtual architecture mapping: A systemc based methodology for architectural exploration of system-on-chips. In IJES, Vol. 3, Nr. 3, pages 150–159, 2008.

    Google Scholar 

  10. Texas Instruments Inc. TMS320C55x DSP CPU Reference Guide (Rev. F). User Guide, Feb. 2004.

    Google Scholar 

  11. Texas Instruments Inc. TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. H). User Guide, Oct. 2008.

    Google Scholar 

  12. Texas Instrument. DSP Libraries for TMS320C64x and TMS320C55x. http://www.ti.com/, Jan. 2011.

  13. K. Kennedy and J.R. Allen. Optimizing Compilers for Modern Architectures: A Dependence-based Approach. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 2002.

    Google Scholar 

  14. S.S. Muchnick. Advanced Compiler Design and Implementation. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 1997.

    Google Scholar 

  15. M. Hohenauer, R. Leupers, O. Wahlen, et al. An executable intermediate representation for retargetable compilation and high-level code optimization. In International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS), 2003.

    Google Scholar 

  16. L. Gao, J. Huang, J. Ceng, R. Leupers, G. Ascheid, and H. Meyr. TotalProf: A fast and accurate retargetable source code profiler. In International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS 2009), Grenoble, France, 2009.

    Google Scholar 

  17. F. Petrot. Automatic timing annotation of native software for mpsoc simulation. In MPSoC’08, June 2008.

    Google Scholar 

  18. The MathWorks Inc. MATLAB. http://www.mathworks.com/, Jan. 2011.

  19. MIL-STD-188-110B Departement of Defense Interface Standard. April 2000.

    Google Scholar 

  20. H. Meyr, M. Moeneclaey, and S.A. Fechtel. Digital Communication Receivers: Synchronization, Channel Estimation and Signal Processing. Wiley, New York, Feb. 1997.

    Google Scholar 

  21. Tensilica Inc. Diamond Standard Processor Core Family Architecture. White Paper, July 2007.

    Google Scholar 

  22. A. Viterbi. Error bounds for convolutional codes and an asymptotically optimum decoding algorithm. IEEE Transactions on Information Theory, 13(2):260–269, 1967.

    Article  MATH  Google Scholar 

  23. C. Berrou and A. Glavieux. Near optimum error correcting coding and decoding: Turbo-codes. IEEE Transactions on Communications, 44(10):1261–1271, Oct. 1996.

    Article  Google Scholar 

  24. Texas Instruments. TMS320C645x DSP Viterbi-Decoder Coprocessor 2 Reference Guide. http://www.ti.com/litv/pdf/spru972, April 2006.

  25. Texas Instruments. DSP Libraries for TMS320C64x and TMS320C55x. http://www.ti.com/, Jan. 2011.

  26. Texas Instruments. Reed Solomon Decoder: TMS320C64x Implementation, December 2000.

    Google Scholar 

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Correspondence to Torsten Kempf .

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Kempf, T., Ascheid, G., Leupers, R. (2011). Case Study. In: Multiprocessor Systems on Chip. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-8153-0_8

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  • DOI: https://doi.org/10.1007/978-1-4419-8153-0_8

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