Micro Bump Assembly

Abstract

One of the key technologies for enabling 3D integration of semiconductor devices is the micro bump based interconnect joining that allows silicon dies with through-silicon vias (TSVs) to be stacked on each other. In order to achieve a high level of integration, the pitch and dimensions of these micro bumps also need to be reduced. Significant assembly challenges need to be overcome in order to accomplish successful yielding micro bump assemblies. In this chapter, the assembly aspects of micro bump fabrication, joining and underfill integration are discussed. The metallurgical fundamentals of micro bump formation are discussed in order to give insight into the choice of interconnect bonding method, the under bump metallisation and the micro bump as such and the impact of these on the stacking approach. Finally, various stacking schemes for 3D integration are considered and their relative advantages and drawbacks are discussed.