Automated Transistor Sizing for FPGAs

Abstract

The large area, performance and power gap between FPGAs and ASICs reported in the previous chapter clearly demonstrates the need for continued research aimed at narrowing this gap. While narrowing the gap will certainly require innovative improvements to FPGA architectures, it is also instructive to gain a more thorough understanding of the existing gap and the trade-offs that can be made with current architectures. This offers a complementary approach for closing the gap. The navigation of the gap by exploring these trade-offs is the focus of the remainder of this book. This exploration will consider the three central aspects of FPGA design: logical architecture, circuit design and transistor sizing. The challenge for such an exploration is that transistor sizing for FPGAs has been performed manually in most past works [35, 9, 101] and that has limited the scope of those previous investigations. To enable broader exploration in this work, an automated approach for transistor sizing of FPGAs was developed and that is the subject of this chapter.