Today's semiconductor products are more complex and highly integrated due to the increasing demands for system-on-chip solution, which results in a significant increase in time, cost and complexity of testing. Testing of semiconductors has become a significant and growing problem in the very-large-scale-integration (VLSI) circuit manufacturing industry [1, 2]. Semiconductor testing issues such as smaller pad size, increased pad density, increased signal input/output (I/O) frequencies, longer test times, and probe card contact and alignment are restricting the progress towards smaller, faster, and more economical integrated circuits [3].
Conventional wafer probing techniques utilize probe tips to contact the deviceunder- test (DUT) physically and have the limitations of the number of pads, pitch sizes, operating frequency, parallel testing capability and risk of damage to the DUT. Moreover, the calibration of probe tips and silicon substrate especially for highspeed RF circuits have made testing more complicated and may affect the accuracy of testing.
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Wang, Y., Niknejad, A.M., Gaudet, V., Iniewski, K. (2009). CMOS IR-UWB Transceiver System Design for Contact-Less Chip Testing Applications. In: Tasić, A., Serdijn, W.A., Larson, L.E., Setti, G. (eds) Circuits and Systems for Future Generations of Wireless Communications. Series on Integrated Circuits and Systems. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-9917-5_5
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