Integrated Prototypes Using Averaging

This chapter describes two ADCs which employ averaging to reduce the offset voltages of its constituting sub-blocks. The first one, described in section 4.2, is a 7-bit 120 MS/s flash ADC to be used in a satellite receiver. Since the specified maximum input frequency was not very large (about 40 MHz), it was decided not to use a S/H. In this case, as will be seen, the bandwidth of the pre-amplifier must be several times larger than the maximum input frequency, to maintain the distortion in acceptable levels.

The second converter, described in section 4.3, is a 10-bit 100 MS/s folding and interpolation ADC. Cascaded folding stages and interpolation are used to reduce, respectively, the number of latched comparators and input differential pairs. A S/H samples the input signal, provides amplification by 1.5 and maintains the output voltage stable during half clock cycle.