Different MOS transistor models and their basic characteristics are discussed in the beginning of this chapter. The requirements that a MOS model must fulfill to be suitable for the design at the transistor level are identified. Then, an overview of transistor parameters needed for design of analog structures is provided. Finally, a transistor-level design approach based on the choice of the inversion factor and the transistor length is proposed. It includes the design recipes for hand-calculations, and the analyses of parameter limits and parameter optima.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Bibliography
P. Bendix, “Spice model quality: process development viewpoint”,International Symposium on Quality Electronic Design, pp. 477–481,March 2001
P. Bendix, D. Foty, D. Pachura, “Practical aspects of MOS transistormodel “accuracy” in modern CMOS technology”, IEEE International Conference on Electronics, Circuits and Systems, pp. 642–645,December 2004
Y. Tsividis, K. Suyama, “MOSFET modeling for analog circuit CAD:problems and prospects”, IEEE Journal of Solid-State Circuits, Volume 29, pp. 210–216, March 1994
SMARTSpice/UTMOST III, Modeling Manual, Volume 1, SILVACO International, March 1995
BSIM model official site: www-device.eecs.berkeley.edu/̃bsim3
Y. Cheng, C. Hu, “MOSFET Modeling and BSIM3 User's Guide”,Kluwer Academic Publishers, 1999, ISBN 0792385756
EKV model official site: legwww.epfl.ch/ekv
Ch. Enz, F. Krummenacher, E. Vittoz, “An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications”, Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers, pp. 83–114, July 1995
PHILIPS models site: www.nxp.com/Philips_Models/mos_models
R. Velghe, D. Klaassen, F. Klaassen, “Compact MOS modeling for analog circuit simulation”, International Electron Devices Meeting,Technical Digest, pp. 485–488, December 1993
P. Woerlee, M. Knitel, R. van Langevelde, D. Klaassen, L. Tiemeijer, A.Scholten, A. Zegers-van Duijnhoven, “RF-CMOS performance trends”,IEEE Transactions on Electron Devices, Volume 48, pp. 1776–1782,August 2001
G. Gildenblat, W. Hailing, C. Ten-Lon, G. Xin, C. Xiaowen, “SP: an advanced surface-potential-based compact MOSFET model”, IEEE Journal of Solid-State Circuits, Volume 39, pp. 1394–1406, September 2004
PSP model official site: pspmodel.asu.edu
W. Grabinski, B. Nauwelaers, D. Schreurs, “Transistor Level Modeling for Analog/RF IC Design”, chapter 2, Springer, 2006, ISBN 1402045557
Y. Tsividis, “Operation and Modeling of the MOS Transistor”, Oxford University Press, second edition, 2003, ISBN 0195170148
“The EPFL-EKV MOSFET Model Equations for Simulations”,Technical Report, Model Version 2.6, June 1997
M. Bucher, Analytical MOS Transistor Modelling for Analog Circuit Simulation, PhD thesis N°2114, Ecole Polytechnique Fédérale de Lausanne, Lausanne, Switzerland, 1999
J.-M. Sallese, M. Bucher, F. Krummenacher, P. Fazan, “Inversion charge linearization in MOSFET modeling and rigorous derivation of the EKV compact model”, Solid-State Electronics, Volume 47, pp. 677–683, April 2003
Ch. C. Enz, E. A. Vitoz, “Charge-based MOS Transistor Modeling: The EKV Model for Low-power and RF IC Design”, John Wiley & Sons,first edition, 2006, ISBN 9780470855416
D. Binkley, M. Bucher, D. Foty, “Design-oriented characterization of CMOS over the continuum of inversion level and channel length”, IEEE International Conference on Electronics, Circuits and Systems, pp. 161–164, December 2000
M. Bucher, D. Kazazis, F. Krummenacher, D. Binkley, D. Foty, Y.Papananos, “Analysis of transconductances at all levels of inversion in deep submicron CMOS”, International Conference on Electronics,Circuits and Systems, Volume 3, pp. 1183–1186, September 2002
D. Foty, M. Bucher, “Re-interpreting the MOS transistor via the inversion coefficient and the continuum of gms/Id”, International Conference on Electronics, Circuits and Systems, Volume 3, pp. 1179–1182, September 2002Bibliography
Rights and permissions
Copyright information
© 2008 Springer Science+Business Media B.V
About this chapter
Cite this chapter
(2008). Transistor level design. In: Structured Analog CMOS Design. Analog Circuits and Signal Processing. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-8573-4_2
Download citation
DOI: https://doi.org/10.1007/978-1-4020-8573-4_2
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-8572-7
Online ISBN: 978-1-4020-8573-4
eBook Packages: EngineeringEngineering (R0)