Abstract
Conventional ATPG algorithms would fail when applied to asynchronous circuits due to the absence of a global clock and presence of more state holding elements that synchronize the control and data paths, leading to poor fault coverage. This paper presents three DFT implementations for the asynchronous NULL Conventional Logic (NCL) paradigm, with the following salient features: 1) testing with commercial DFT tools is shown to be feasible; 2) this yields a high test coverage; and 3) minimal area overhead is required. The first technique incorporates XOR gates for inserting test points; the second method uses a scan latch scheme for improving observability; and in the third scheme, scan latches are inserted in the internal gate feedback paths. The approaches have been automated, which is essential for large systems; and are fully compatible with industry standard tools.
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Satagopan, V., Bhaskaran, B., Al-Assadi, W.K., Smith, S.C., Kakarla, S. (2007). Design for Test Techniques for Asynchronous NULL Conventional Logic (NCL) Circuits. In: Elleithy, K. (eds) Advances and Innovations in Systems, Computing Sciences and Software Engineering. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-6264-3_78
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DOI: https://doi.org/10.1007/978-1-4020-6264-3_78
Publisher Name: Springer, Dordrecht
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