Skip to main content
SpringerLink
Log in
Book cover

Encyclopedia of Parallel Computing pp 1223–1232Cite as

Multi-Threaded Processors

  • Reference work entry

  • 189 Accesses

Synonyms

Multi-streamed processors

Definition

Opposed to standard single-threaded processors, in which only one software thread can be present and executed at any given time, Multithreaded Processors can hold multiple software threads which can be running simultaneously. The amount of information needed to be held per software thread is defined as the context. Therefore, a processor that can hold multiple contexts concurrently is defined as a Multithreaded Processor.

Discussion

Introduction

In the continuing search for a higher level of performance, computer architects have been consistently pushing the speed of the system and the microarchitecture design. For instance, microprocessor speeds in the last 40 years have grown by 4,000 times while the instructions per clock have increased from 0.125 on the Intel 4004 to at least 3 per core on the Intel Xeons which have a 64-bit data width compared to the 4-bit 4004. Yet, the semiconductor technology and microarchitecture innovations that...

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   1,600.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD   1,799.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Bibliography

  1. Agarwal A et al (1993) Sparcle: an evolutionary processor design for large-scale multiprocessors. IEEE Micro 13:48–61

    Article  Google Scholar 

  2. Anderson W (2005) Experiences using the cray multi-thread architecture (MTA 2). 2003 user group conference (DoD UGC’03), Bellevue, ISBN: 0-7695-1953-9

    Google Scholar 

  3. Chapell R et al (1999) Simultaneous subordinate microthreading (SSMT). In: Proceedings of the 26th annual international symposiumon computer architecture, Atlanta, GA. IEEE Computer Society Washington, DC, pp 186–195

    Google Scholar 

  4. Dubey P et al (1995) Single-program speculative multithreading (SPSM) architecture: compiler-assisted fine-grain multithreading. Tech. Rep. RC 19928. IBM, Yorktown Heights, NY

    Google Scholar 

  5. Emer J (1999) Simultaneous multithreading: multiplying aspha’s performance. In: Proceedings of the microprocessor forum, San Jose, CA

    Google Scholar 

  6. Espasa R, Valero M (1997) Exploiting instruction- and data-level parallelism. IEEE MICRO 17(5):20–27

    Article  Google Scholar 

  7. Grunewald W, Ungerer T (1997) A multithreaded processor designed for distributed shared memory systems. In: Proceedings of the international conference on advances in parallel and distributed computing, APDS-97, Shanghai

    Google Scholar 

  8. Halstead Jr RH (1988) MASA: a multithreaded processor architecture for parallel symbolic computing. ACM SIGARCH Computer Architecture News 16(2):443–451

    Article  Google Scholar 

  9. Hirata H et al (1992) An elementary processor architecture with simultaneous instruction issuing from multiple threads. In: Proceedings of the 19th international symposium of computer architecture, Gold Coast, Australia. ACM Press, New York, pp 135–145

    Google Scholar 

  10. http://www.opensparc.net

  11. http://www.pcworld.com/article/105126/sun_hints_at_ultrasparc _v_and_beyond.html

  12. http://www.zytek.com/∼melvin/clearwater.html

  13. Iannucci R, Gao G, Halstead R Jr, Smith B (1994) Multithreaded computer architecture: a summary of the state of the art. The Springer International Series in Engineering and Computer Science. Kluver, Norwell, ISBN 0-7923-9477-1

    Book  Google Scholar 

  14. Jordan HF (1983) Performance measurements on HEP – a pipelined MIMD computer. In: Proceedings of the 10th annual international symposium on computer architecture. IEEE, New York, ISBN 0-89791-101-6

    Google Scholar 

  15. Keckler SW, Dally WJ et al (1995) The M-machine multicomputer. In: Proceedings of the 28th annual international symposium on computer architecture, Ann Arbor, MI. ACM Press, New York, pp 146–156

    Google Scholar 

  16. Marr D et al (2002) Hyper-threading technology architecture and microarchitecture: a hypertext history. Intel Technol J 6(1)

    Google Scholar 

  17. Metzner A, Niehaus J (2000) MSparc: multithreading in real-time architectures. J Univ Comput Sci 6(10):1034–1051

    MATH  Google Scholar 

  18. Nemirovsky et al (1992) Microprogrammed timer processor. US patent 5117387

    Google Scholar 

  19. Nemirovsky M, Brewer F, Wood R (1991) DISC: dynamic instruction stream computer. In: Proceedings of the 24th annual international symposium on microarchitecture. Albuquerque, New Mexico

    Google Scholar 

  20. Noakes MD, Wallach DA, Dally WJ (1993) The J-machine multicomputer: an architectural evaluation. In: Proceedings of the 20th annual international symposium on computer architecture, San Diego, CA. ACM Press, New York, pp 224–235

    Chapter  Google Scholar 

  21. Smith B (1985) On parallel MIMD computation: HEP supercomputer and its applications. Massachusetts Institute of Technology, Cambridge, MA, ISBN 0-262-11101-2

    Google Scholar 

  22. Smith BJ (1978) A pipelined, shared resource MIMD computer. In: Proceedings of the 1978 international conference on parallel processing. IEEE press, Piscataway, pp 6–8

    Google Scholar 

  23. Sohi G, Breach S, Vijaykumar T (1995) Multiscalar processor. In: Proceedings of the 22nd annual international symposium on computer architecture, Santa Margherita Ligure, Italy, June 1995. Kluwer, Norwell, pp 414–425

    Google Scholar 

  24. Thistle MR, Smith BJ (1988) A processor architecture for horizon. In: Proceedings of the 1988 ACM/IEEE conference on supercomputing, Orlando, FL. IEEE Computer Society Press, Los Alamitos, pp 35–41

    Google Scholar 

  25. Thornton JE (1970) Design of a computer – the control data 6600. Scott, Foresman and Co, Glenview

    Google Scholar 

  26. Tullsen D, Eggers S, Levy H (1995) Simultaneous multithreading: maximizing on chip parallelism. In: Proceedings of the 22nd annual international symposium on computer architecture, Santa Margherita Ligure, Italy, June 1995. Kluwer, Norwell, pp 392–403

    Google Scholar 

  27. Ungerer T, Bobic B, Silc J (2003) A survey of processor with Explicit Multithreading. ACM Comput Surv (CSUR) 35(1):29–63

    Article  Google Scholar 

  28. Wallace S, Calder B, Tullsen D (1998) Threaded multiple path execution. In: Proceedings of the 25th annual international symposiumon computer architecture, Barcelona, Spain. IEEE Computer Society Washington, DC, pp 238–249

    Google Scholar 

  29. Yamamoto W, Nemirovsky M (1995) Increasing superscalar performance through multistreaming. In: Proceedings of the international conference on parallel architectures and compilation techniques, Limassol, Cyprus. IEEE Computer Society Washington, DC, pp 49–58

    Google Scholar 

  30. Yamamoto W, Serrano M, Wood R, Nemirovsky M (1994) Performance estimation of multistreamed superscalar processors. In: Proceedings of the Hawaii conference on systems and science, Hawaii, January 1994. IEEE Computer Society, Los Alamitos, pp 195–204

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. ICREA, Computer Sciences – Network Processors, Barcelona Supercomputer Center, Barcelona, Spain

    Mario Nemirovsky Dr., Professor

Authors
  1. Mario Nemirovsky Dr., Professor
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. University of Illinois at Urbana-Champaign, Urbana, IL, USA

    David Padua

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer Science+Business Media, LLC

About this entry

Cite this entry

Nemirovsky, M. (2011). Multi-Threaded Processors. In: Padua, D. (eds) Encyclopedia of Parallel Computing. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-09766-4_423

Download citation

Publish with us

Policies and ethics

Search

Navigation