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An integer linear programming model of software pipelining for the MIPS R8000 processor

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Parallel Computing Technologies (PaCT 1997)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1277))

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Abstract

In parallelizing the code for high-performance processors, software pipelining of innermost loops is of fundamental importance. In order to benefit from software pipelining, two separate tasks need to be performed: (i) software pipelining proper (find the rate-optimal legal schedule), and (ii) register allocation (allocate registers to the found schedule). Software pipelining and register allocation can be formulated as an integer linear programming (ILP) problem, aiming to produce optimal schedules. In this paper, we discuss the application of the integer linear programming to software pipelining on the MIPS R8000 superscalar microprocessor. Some of the results were presented in the PLDI96 [14], where they were compared to the MIPSpro software pipeliner. In this paper we further extend the ILP model for the MIPS R8000 by including memory optimization and present the entire model in detail.

important part of this work was done while in McGill University in Montreal

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Authors and Affiliations

  1. EE Department, University of Delaware, USA

    Artour Stoutchinin

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  1. Artour Stoutchinin
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Victor Malyshkin

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© 1997 Springer-Verlag Berlin Heidelberg

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Stoutchinin, A. (1997). An integer linear programming model of software pipelining for the MIPS R8000 processor. In: Malyshkin, V. (eds) Parallel Computing Technologies. PaCT 1997. Lecture Notes in Computer Science, vol 1277. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-63371-5_14

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  • DOI: https://doi.org/10.1007/3-540-63371-5_14

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-63371-6

  • Online ISBN: 978-3-540-69525-7

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