Abstract
We present a case study of the use of formal verification methods in a computer system design project. The SMV model checker was integrated into the project design flow, and used to verify a specification of a cache coherency protocol for a directory based, distributed shared memory, machine. Both the processor and I/O portions of the protocol specification were verified, within the strict time schedule of the overall project.
We consider the following to be the main benefits to using the SMV model checker: it allows the verification of the interaction of the processors and I/O, early in the design phase; and most importantly it uncovered several protocol specification problems. One problem it uncovered, would never have been found in simulation, and because of its subtle symptoms, loss of coherency, might not have been found on the test floor.
Chapter PDF
Similar content being viewed by others
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
References
S. V. Adve, “Designing Memory Consistency Models For Shared-Memory Multiprocessors”, Ph.D. Thesis, U of Wisconsin-Madison, 1993.
R. E. Bryant, “Graph Based Algorithms for Boolean Function Manipulation”, IEEE Trans. on Comp., C-35, pp. 677–681, 1986.
R. E. Bryant, D. L. Beatty, and C. J. Seger, “Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation”, Proc. 28th ACM/IEEE Design Automation Conf., 1991
E. M. Clarke, O. Grumberg, H. Hirashi, S. Jha, D.E. Long, K.L. McMillan, and L. A. Ness, “Verification of the Futurebus+ cache coherence protocol”, Proc. 11th Intl. Symp. on Computer. Hardware Description. Lang. and their Application, 1993
W. W. Collier, “Reasoning about Parallel Architectures”, Prentice-Hall, Englewood Cliffs, New Jersey, 1992
M. Galles, E. Williams, “Performance Optimization, Implementation, and Verification of the SGI Challenge Multiprocessor”, Hot Chips Symposium, Stanford, 1993.
K. Gharachorloo, D. Lenoski, J.Laudon, P. Gibbons, A. Gupta, and J. Hennessy, “Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors”, Proc. 17th Ann Int'l Symp. on Computer Architecture, ACM, pp. 15–26, 1990.
K. Gharachorloo, S. V. Adve, A. Gupta, J. L. Hennessey, and M. D. Hill, “Specifying System Requirements for Memory Consistency Models”, University of Wisconsin-Madison Comp. Sci. Tech: Report #1199.
M. J. C. Gordon (ed), “HOL: A Proof-Generating System for Higher-Order Logic”, Kluwer SECS 35, pp. 73–128, 1988.
A. Gupta, “Formal Hardware Verification Methods: A Survey”, Formal Methods in System Design”, Vol. 1, 2/3, pp. 5–92, Oct. 1992.
Joe Heinrich, “MIPS R10000 Microprocessor User's Manual”, MIPS Technologies, Inc., 2011 N. Shoreline, Mountain View, CA, 1994
R. P. Kurshan, “Computer-Aided Verification of Coordinating Processes: The Automata-Theoretic Approach”, Princeton University Press, 1994
D. Lenoski, J. Laudon, K. Gharachorloo, W.-D Weber, A. Gupta, J. Hennessy, M. Horowitz, M. Lam, “The Stanford Dash Multiprocessor”, IEEE Computer, vol. 25, pp. 63–79, March 1992.
D. E. Long, “Model Checking, Abstraction and Compositional Verification”, Ph.D. Thesis, CMU 1993
K. L. McMillan, J. Schwalbe, “Formal Verification of the Encore Gigamax cache consistency protocol.”, Int. Symposium on Shared Memory Multiprocessors, 1991.
K. L. McMillan, “Symbolic Model Checking”, Kluwer Academic Publishers, 1993
C. J. Seger, R. E. Bryant, “Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories”, Tech. Report 93-8, Dept. of Computer Science, University of British Columbia, Aug. 1993.
A. S. Tanenbaum, “Distributed Operating Systems”, Prentice-Hall, 1995
M. Yoeli, “Formal Verification of Hardware Design”, IEEE Computer Society Press, Los Alamitos, CA 1990.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1995 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Eiríksson, Á.T., McMillan, K.L. (1995). Using formal verification/analysis methods on the critical path in system design: A case study. In: Wolper, P. (eds) Computer Aided Verification. CAV 1995. Lecture Notes in Computer Science, vol 939. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-60045-0_63
Download citation
DOI: https://doi.org/10.1007/3-540-60045-0_63
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-60045-9
Online ISBN: 978-3-540-49413-3
eBook Packages: Springer Book Archive