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OR causality: Modelling and hardware implementation

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Application and Theory of Petri Nets 1994 (ICATPN 1994)

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Abstract

Asynchronous circuits behave like concurrent programs implemented in hardware logic. The processes in such circuits are synchronised in accordance with the dynamic logical and causal conditions between switching events. In this paper we investigate a paradigm called OR causality. Petri nets and Change Diagrams provide adequate modelling and circuit synthesis tools for the various OR causality types, yet they do not always bring the specifier to a unique decision about which modelling construct must be used for which type. We present a unified descriptive tool, called Causal Logic Net, which is graphically based on Petri net but has an explicit logic causality annotation for transitions. The signal-transition interpretation of this tool is analogous to, but more powerful than, the well-known Signal Transition Graph. A number of examples demonstrate the usefulness of this model in the synthesis of asynchronous control circuits.

This work has been partly supported by SERC GR/J52327.

This work has been supported by The Danish Technical Research Council.

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References

  1. T.-A. Chu. On the models for designing vlsi asynchronous digital systems. Integration: the VLSI journal, 4:99–113, 1986.

    Google Scholar 

  2. F Commoner, A.W. Holt, S. Even, and A. Pnueli. Marked directed graphs. Journal of Computer and Systems Sciences, 5:511–523, 1971.

    Google Scholar 

  3. H.J. Genrich and R.M. Shapiro. Formal verification of an arbiter cascade. In Proceedings of 13th Int. Conferenece on Application and Theory of Petri Nets, Lecture Notes in Computer Science, Springer-Verlag, Berlin, 1992.

    Google Scholar 

  4. J. Gunawardena. Causal automata. Theoretical Computer Science, 101(2):265–288, 1992.

    Article  Google Scholar 

  5. M. Kishinevsky, A. Kondratyev, A. Taubin, and V. Varshavsky. Concurrent Hardware: The Theory and Practice of Self-Timed Design. John Wiley and Sons, London, 1993.

    Google Scholar 

  6. L. Lavagno and A. Sangiovanni-Vincentelli. Algorithms for Synthesis and Testing of Asynchronous Circuits. Kluwer Academic Publishers, Boston, 1993.

    Google Scholar 

  7. D. Muller and W. Bartky. A theory of asynchronous circuits. In Annals of Computation Laboratory, pages 204–243. Harvard University, 1959.

    Google Scholar 

  8. J.L. Peterson. Petri Net Theory and Modeling of Systems. Prentice-Hall, Englewood Cliffs, N.J., 1981.

    Google Scholar 

  9. Marta Pietkiewicz-Koutny. Proof of the conjecture that the language generated by a certain Change Diagram cannot be generated by Petri nets. Manuscript, Feb. 1994.

    Google Scholar 

  10. L.Ya. Rosenblum and A.V. Yakovlev. Signal graphs: from self-timed to timed ones. In Proceedings of International Workshop on Timed Petri Nets, Torino, Italy, July 1985, pages 199–207. IEEE Computer Society, 1985.

    Google Scholar 

  11. Patil S.S. and J.B. Dennis. The description and realization of digital systems. In: Innovative Architectures. IEEE, N.Y., 1972.

    Google Scholar 

  12. V. Varshavsky, M. Kishinevsky, V. Marakhovsky, V. Peschansky, L. Rosenblum, A. Taubin, and B. Tzirlin. Self-Timed Control of Concurrent Processes. Kluwer AP, Dordrecht, 1990.

    Google Scholar 

  13. V.I. Varshavsky, M.A. Kishinevsky, A.Y. Kondratyev, L.Y. Rosenblyum, and A.R. Taubin. Models for specification and analysis of processes in asynchronous circuits. Soviet Journal of Computer and System Sciences, 26(2):61–76, 1989. Russian Edition — 1988.

    Google Scholar 

  14. A. Yakovlev, M. Kishinevsky, A. Kondratyev, and L. Lavagno. On the models for asynchronous circuit behaviour with OR causality. TR-463, University of Newcastle upon Tyne, November 1993.

    Google Scholar 

  15. A. Yakovlev, L. Lavagno, and A. Sangiovanni-Vincentelli. A unified STG model for asynchronous control circuit synthesis. In Proceedings of ICCAD '92, Santa Clara, CA, November 1992.

    Google Scholar 

  16. A Yakovlev, A. Petrov, and L. Lavagno. High speed asynchronous arbiter. TR-427, University of Newcastle upon Tyne Computing Science, May 1993.

    Google Scholar 

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Robert Valette

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© 1994 Springer-Verlag Berlin Heidelberg

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Yakovlev, A., Kishinevsky, M., Kondratyev, A., Lavagno, L. (1994). OR causality: Modelling and hardware implementation. In: Valette, R. (eds) Application and Theory of Petri Nets 1994. ICATPN 1994. Lecture Notes in Computer Science, vol 815. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58152-9_31

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  • DOI: https://doi.org/10.1007/3-540-58152-9_31

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  • Print ISBN: 978-3-540-58152-9

  • Online ISBN: 978-3-540-48462-2

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