Abstract
Due to technology scaling, the trend for integrated circuits is towards higher power dissipation, higher frequency and lower supply voltages. As a result, the power supply current delivered through the on-chip power grid is increasing dramatically, which is recognized in the International Technology Roadmap for Semiconductors as a difficult challenge. Early power grid design and the addition of decoupling capacitance have become crucially important to control power-grid- induced noise. We show analytical relationships and simulation results that highlight key relationships between noise and technology parameters. The results underline trends in noise based on current roadmap predictions and reinforce the importance of early planning of global power grids.
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Carballo, JA., Nassif, S.R. (2002). Impact of Technology in Power-Grid-Induced Noise. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_5
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DOI: https://doi.org/10.1007/3-540-45716-X_5
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