Abstract
This paper presents an experimental study of register file utilization in conventional RISC-type data path architecture to determine benefits that we can expect to achieve by eliminating unnecessary register file reads and writes. Our analysis shows that operand bypassing, enhanced for operand-reuse can discard the register file accesses up to 65% as a peak and by 39% on average for tested benchmark programs.
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© 2002 Springer-Verlag Berlin Heidelberg
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Takamura, H., Inoue, K., Moshnyaga, V.G. (2002). Register File Energy Reduction by Operand Data Reuse. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_28
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DOI: https://doi.org/10.1007/3-540-45716-X_28
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