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Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level

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Book cover Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation (PATMOS 2002)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2451))

Abstract

Accurate estimation of switching activity is very important in digital circuits. In this paper we present a comparison between the evaluation of the switching activity calculated using logic (Verilog) and electrical (HSPICE) simulators. We also study how the variation on the delay model (min, typ, max) and parasitic effects affect the number of transitions in the circuit. Results show a variable and significant overestimation of this measurement using logic simulators even when including postlayout effects. Furthermore, we show the contribution of glitches to the overall switching activity, giving that the treatment of glitches in conventional logic simulators is the main cause of switching activity overestimation.

This work has been sponsored by MCYT of Spain under Projects TIC2000-1350 and TIC2001/2283

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References

  1. A. Ghosh, S. Devadas, K. Keutzer, and J. White: “Estimation of Average Switching Activity in Combinational and Sequential Circuits”. Proc. 29th Design Automation Conference, pp. 253–259. June 1992.

    Google Scholar 

  2. J. Monteiro, S. Devadas, and B. Lin: “A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits”. Proc. 31th Design Automation Conference, pp. 12–17. Jun. 1994.

    Google Scholar 

  3. X. Aragonès, J. L. González and A. Rubio, “Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs”. Kluwer Academic Publishers, 1999.

    Google Scholar 

  4. D.J. Allstot, S-H. Chee and M. Shrivastawa, “Folded Source-Coupled Logic vs. CMOS Static Logic for Low-Noise Mixed-Signal ICs”, IEEE Trans. Circuits and Systems I, Vol. 40, pp. 553–563, Sept. 1993.

    Google Scholar 

  5. Y. Tsividis, “Mixed Analog-Digital VLSI Design and Technology”. McGraw-Hill, 1995.

    Google Scholar 

  6. E. Melcher, W. Röthig, M. Dana. “Multiple Input Transitions in CMOS Gates”. Microprocessing and Microprogramming 35 (1992) pp. 683–690. North Holland.

    Article  Google Scholar 

  7. C. Metra, M. Favalli, B. Riccò. “Glitch power dissipation model”. In Proc. PATMOS’95. pp. 175–189

    Google Scholar 

  8. M. Eisele, J. Berthold. “Dynamic Gate Delay Modeling for Accurate Estimation of Glitch Power at Logic Level”. In Proc. PATMOS’95. pp. 190–201. 1995.

    Google Scholar 

  9. M.J. Bellido, J. Juan-Chico, A.J. Acosta, M. Valencia and J.L. Huertas: “Logical modeling of delay degradation effect in static CMOS gates”. IEE Proc. Circuits Devices Sist., Vol. 147, N°2, pp. 107–117. April 2000.

    Google Scholar 

  10. G. Jochens, L. Kruse and W. Nebel: “Application of toggle-based power estimation to module characterization”. In Proc. PATMOS’97. pp. 161–170. 1997.

    Google Scholar 

  11. D. Rabe, G. Jochens, L. Kruse and W. Nebel. “Power-simulation of cell based ASICs: accuracy-and performance trade-offs”. In Proc. DATE’98. pp. 356–361. 1998.

    Google Scholar 

  12. D. Bryan and H. Fujiwara: “A neutral netlist of 10 Combinational Benchmark Circuits and a target Translator in Fortran”. IEEE International Symposium on Circuits and Systems, pp. 695–698. June, 1985.

    Google Scholar 

  13. L. Wall, T. Christiansen and R. L. Schwartz, “Programming PERL”. O’Reilly, 1996.

    Google Scholar 

  14. F. N. Najm: “A Survey of Power Estimation Techniques in VLSI Circuits”. IEEE Transactions on VLSI Systems, Vol. 2, num. 4, pp. 446–455. Dec. 1994.

    Article  Google Scholar 

  15. J. Juan-Chico, M.J. Bellido, P. Ruiz-de-Clavijo, A.J. Acosta and M. Valencia: “Gate-Level Modeling of the Delay Degradation Effect”. Proc. 15th DCIS, pp. 537–542, Nov. 2000.

    Google Scholar 

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Author information

Authors and Affiliations

  1. Instituto de Microelectrónica de Sevilla-CNM, Universidad de Sevilla, Avda. Reina Mercedes s/n, 41012, Sevilla, SPAIN

    C. Baena, J. Juan-Chico, M. J. Bellido, P. Ruiz de Clavijo, C. J. Jiménez & M. Valencia

Authors
  1. C. Baena
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  2. J. Juan-Chico
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  3. M. J. Bellido
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  4. P. Ruiz de Clavijo
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  5. C. J. Jiménez
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  6. M. Valencia
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Editor information

Editors and Affiliations

  1. Ecole d’Ingénieurs du Canton de Vaud Microelectronics and Systems Institute, Digital Communications Team, Swiss University of Applied Science, Rue de Galilée 15, 1400, Yverdon, Switzerland

    Bertrand Hochet

  2. Instituto de Microelectrónica de Sevilla-CNM-CSIC Departamento do Diseño Digital Departamento de Electrónica y Electromagnetismo Departamento de Tecnología Electrónica, Universidad de Sevilla, Avda. Reina Mercedes, s/n. Edif. CICA

    Antonio J. Acosta  & Manuel J. Bellido  & 

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© 2002 Springer-Verlag Berlin Heidelberg

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Baena, C., Juan-Chico, J., Bellido, M.J., de Clavijo, P.R., Jiménez, C.J., Valencia, M. (2002). Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_35

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  • DOI: https://doi.org/10.1007/3-540-45716-X_35

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-44143-4

  • Online ISBN: 978-3-540-45716-9

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