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International Conference on Parallel Problem Solving from Nature

PPSN 2000: Parallel Problem Solving from Nature PPSN VI pp 671–680Cite as

A Genetic Algorithm for VLSI Floorplanning

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1917))

Abstract

We present a genetic algorithm (GA) which uses a normalized postfix encoding scheme to solve the VLSI floorplanning problem. We claim to have overcome the representational problems previously associated with encoding postfix expressions into GAs, and have developed a novel encoding system which preserves the integrity of solutions under all the genetic operators. Optimal floorplans are obtained for module sets taken from some MCNC benchmarks. The slicing tree construction process, used by our GA to generate the floorplans, has a run time scaling which compares very favourably with other recent approaches.

This work was partially supported by NASA grant NAG-5-4868.

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Author information

Authors and Affiliations

  1. Department of Computer Science, Cardiff University, PO Box 916, Cardiff, CF24 3XF, UK

    Christine L. Valenzuela

  2. Department of Computer Science MS4A5, George Mason University, Fairfax, VA, 22030-4444, USA

    Pearl Y. Wang

Authors
  1. Christine L. Valenzuela
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  2. Pearl Y. Wang
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Editor information

Editors and Affiliations

  1. CMAP, Ecole Polytechnique, 91128, Palaiseau Cedex, France

    Marc Schoenauer

  2. Dept. of Mechanical Engineering Kanpur Genetic Algorithms Laboratory, Indian Institute of Technology Kanpur, Kanpur, Pin, 208 016, India

    Kalyanmoy Deb

  3. Fachbereich Informatik, Lehrstuhl für Systemanalyse, Universität Dortmund, Joseph-von-Fraunhofer-Str. 20, 44221, Dortmund, Germany

    Günther Rudolph  & Hans-Paul Schwefel  & 

  4. School of Computer Science, The University of Birmingham, Edgbaston, Birmingham, B15 2TT, UK

    Xin Yao

  5. Projet Fractales, INRIA Rocquencourt, BP 105, 78153, Le Chesnay Cedex, France

    Evelyne Lutton

  6. Dept. de Arquitectura y Technologa de los Computadores, GeNeura Team, Universidad de Granada, Campus Fuenetenueva, s/n, Granada

    Juan Julian Merelo

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© 2000 Springer-Verlag Berlin Heidelberg

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Valenzuela, C.L., Wang, P.Y. (2000). A Genetic Algorithm for VLSI Floorplanning. In: Schoenauer, M., et al. Parallel Problem Solving from Nature PPSN VI. PPSN 2000. Lecture Notes in Computer Science, vol 1917. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45356-3_66

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  • DOI: https://doi.org/10.1007/3-540-45356-3_66

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-41056-0

  • Online ISBN: 978-3-540-45356-7

  • eBook Packages: Springer Book Archive

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