Efficient Self-Reconfigurable Implementations Using On-chip Memory

Abstract

The limited I/O bandwidth in reconfigurable devices results in a prohibitively high reconfiguration overhead for dynamically reconfigured FPGA-based platforms. Thus, the full potential of dynamic reconfiguration can not be exploited. Usually, any attainable speed-up by executing an application on hardware is diminished by the reconfiguration overhead. The self-reconfiguration concept aims at drastically reducing the reconfiguration overhead by performing dynamic reconfiguration on-chip without the intervention of an external host. Thus, using self-reconfiguration, a configurable device can alter its functionality autonomously. Implementations based on self-reconfiguration promise significant speed-up compared with conventional approaches [7,8].

This research was performed as part of the MAARCII project. This work is supported in part by the DARPA Adaptive Computing Systems program under contract no. DABT63-99-1-0004 monitored by Fort Huachuca and in part by the National Science Foundation under grant no. CCR-9900613.