Abstract
Decoupled processing seeks to dynamically schedule memory accesses in order to tolerate memory latency by prefetching operands. Since decoupled processors can not speculatively issue memory operations, control flow operations can significantly impact their ability to prefetch data. The prefetching architecture proposed here seeks to leverage the dynamic scheduling benefits of decoupled processing while allowing memory operations to be speculatively invoked. The prefetching mechanism is evaluated using the SPEC95 suite of benchmarks and significant reductions in cache miss rate are achieved, resulting in speed-ups of over 40% of peak for most of the inputs.
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References
Doug Burger and Todd M. Austin. The SimpleScalar tool set, version 2.0. Technical Report 1342, University of Wisconsin-Madison, 1997.
Tien-Fu Chen. An effective programmable prefetch engine for on-chip caches. In Proceedings of the 28th Annual International Symposium on Microarchitecture, 1995.
T.-C. Chiueh. Sunder: A programmable hardware prefetch architecture for numerical loops. In IEEE, editor, Proceedings, Supercomputing’ 94: Washington, DC, November 14-18, 1994, Supercomputing, pages 488–497, 1109 Spring Street, Suite 300, Silver Spring, MD 20910, USA, 1994. IEEE Computer Society Press.
Kevin D. Rich. Compiler Techniques for Evaluating and Extending Decoupled Architectures. PhD thesis, University of California at Davis, 2000.
Kevin Skadron. Characterizing and Removing Branch Mispredictions. PhD thesis, Princeton University, June 1999.
James E. Smith. Dynamic instruction scheduling and the Astronautics ZS-1. IEEE Computer, 22(7):21–35, July 1989.
N.P. Topham and K. McDougall. Performance of the decoupled ACRI-1 architecture: the Perfect Club. In Proceedings of High Performance Computing-Europe, 1995.
Gary S. Tyson. Evaluation of a Scalable Decoupled Microprocessor Design. PhD thesis, University of California at Davis, 1997.
Steven P. VanderWiel and David J. Lilja. A compiler-assisted data prefetch controller. Technical Report ARCTiC 99-05, University of Minnesota, May 1999.
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Rich, K.D., Farrens, M.K. (2000). The Decoupled-Style Prefetch Architecture. In: Bode, A., Ludwig, T., Karl, W., Wismüller, R. (eds) Euro-Par 2000 Parallel Processing. Euro-Par 2000. Lecture Notes in Computer Science, vol 1900. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44520-X_140
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DOI: https://doi.org/10.1007/3-540-44520-X_140
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