Abstract
A diverse collection of correctness statements have been proposed and used in microprocessor verification efforts. Correctness statements have evolved from criteria that match a single step of the implementation against the specification to seemingly looser, multi-step, criteria. In this paper, we formally verify conditions under which two categories of multi-step correctness statements logically imply single-step correctness statements. The first category of correctness statements compare flushed states of the implementation and the second category compare states that are able to retire instructions. Our results are applicable to superscalar implementations, which fetch or retire multiple instructions in a single step.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
M. D. Aagaard, B. Cook, N. A. Day, and R. B. Jones. A framework for microprocessor correctness statements. In CHARME, volume 2144 of LNCS, pages 433–448. Springer, 2001.
M. D. Aagaard, B. Cook, N. A. Day, and R. B. Jones. A framework for superscalar microprocessor correctness statements, 2002. To appear in Software Tools for Technology Transfer.
T. Arons and A. Pnueli. Verifying Tomasulo’s algorithm by refinement. In Int’l Conf. on VLSI Design, pages 92–99. IEEE Comp. Soc. Press, 1999.
S. Berezin, E. Clarke, A. Biere, and Y. Zhu. Verification of out-of-order processor designs using model checking and a light-weight completion function. Formal Methods in System Design, 20(2): 159–186, March 2002.
J. Burch and D. Dill. Automatic verification of pipelined microprocessor control. In CAV, volume 818 of LNCS, pages 68–80. Springer, 1994.
N. A. Day, M. D. Aagaard, and M. Lou. A mechanized theory for microprocessor correctness statements. Technical Report 2002-11, U. of Waterloo, Dept. of Comp. Sci., 2002.
A. Fox and N. Harman. Algebraic models of correctness for microprocessors. Formal Aspects in Computing, 12(4):298–312, 2000.
M. Gordon and T. Melham. Introduction to HOL: A Theorem Proving Environment for Higher Order Logic. Cambridge University Press, 1993.
R. Hosabettu, G. Gopalakrishnan, and M. Srivas. Verifying advanced microarchitectures that support speculation and exceptions. In CAV, volume 1855 of LNCS, pages 521–537. Springer, 2000.
R. Hosabettu, M. Srivas, and G. Gopalakrishnan. Decomposing the proof of correctness of pipelined microprocessors. In CAV, volume 1427 of LNCS, pages 122–134. Springer, 1998.
R. Hosabettu, M. Srivas, and G. Gopalakrishnan. Proof of correctness of a processor with reorder buffer using the completion functions approach. In CAV, volume 1633 of LNCS, pages 47–59. Springer, 1999.
R. Hosabettu, M. Srivas, and G. Gopalakrishnan. Proof of correctness of a processor without reorder buffer using the completion functions approach. In CHARME, volume 1703 of LNCS, pages 8–22. Springer, 1999.
R. Jones, J. Skakkebæk, and D. Dill. Reducing manual abstraction in formal verification of out-of-order execution. In FMCAD, volume 1522 of LNCS, pages 2–17. Springer, 1998.
R. B. Jones, J. U. Skakkebæk,, and D. L. Dill. Formal verification of out-of-order execution using incremental flushing. Formal Methods in System Design, 20(2):39–58, March 2002.
R. Milner. An algebraic definition of simulation between programs. In Joint Conference on Artificial Intelligence, pages 481–489. British Computer Society, 1971.
J. Sawada and W. Hunt. Trace table based approach for pipelined microprocessor verification. In CAV, volume 1254 of LNCS, pages 364–375. Springer, 1997.
J. Sawada and W. Hunt. Processor verification with precise exceptions and speculative execution. In CAV, volume 1427 of LNCS, pages 135–146. Springer, 1998.
J. Sawada and W. Hunt. Results of the verification of a complex pipelined machine model. In CHARME, volume 1703 of LNCS, pages 313–316. Springer, 1999.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2002 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Aagaard, M.D., Day, N.A., Lou, M. (2002). Relating Multi-step and Single-Step Microprocessor Correctness Statements. In: Aagaard, M.D., O’Leary, J.W. (eds) Formal Methods in Computer-Aided Design. FMCAD 2002. Lecture Notes in Computer Science, vol 2517. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36126-X_8
Download citation
DOI: https://doi.org/10.1007/3-540-36126-X_8
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-00116-4
Online ISBN: 978-3-540-36126-8
eBook Packages: Springer Book Archive