Abstract
Bypass delays are expected to grow beyond 1ns as technology scales. These delays necessitate pipelining of bypass paths at processor frequencies above 1GHz and thus affect the performance of sequential code sequences. We propose dealing with these delays through a dynamic functional unit chaining approach. We study the performance benefits of a superscalar, out-of-order processor augmented with a two-by-two array of ALUs interconnected by a fast, partial bypass network. An online profiler guides the automatic configuration of the network to accelerate specific patterns of dependent instructions. A detailed study of benchmark simulations demonstrates these first steps towards mapping binaries to a small coarse-grained array at runtime can improve instruction throughput by over 18% and 25% when the microarchitecure includes bypass delays of one cycle and two cycles, respectively.
This is a preview of subscription content, log in via an institution to check access.
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
CPU SPEC 2000 Benchmarks, http://www.spec.org
International Technology Roadmap for Semiconductors, http://www.itrs.net
The SimpleScalar Toolset, http://www.simplescalar.com
Hinton, G., Sager, D., Upton, M., Boggs, D., Carmean, D., Kyker, A., Roussel, P.: The Microarchitecture of the Pentium® 4 Processor. Intel Technology Journal Q1 (2001)
Ho, R., Mai, K., Horowitz, M.: The Future of Wires. The Proceedings of the IEEE, 490–504 (April 2001)
KleinOsowski, A.J., Lilja, D.J.: MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research. Computer Architecture Letters 1 (June 2002)
Lee, C., Potkonjak, M., Mangione-Smith, W.H.: MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems. In: International Symposium on Microarchitecture, pp. 330–335 (1997)
Matson, M., Bailey, D., Bell, S., Biro, L., Butler, S., Clouser, J., Farrell, J., Gowan, M., Priore, D., Wilcox, K.: Circuit Implementation of a 600MHz Superscalar RISC Microprocessor. In: International Conference on Computer Design, pp. 104–110 (October 1998)
Palacharla, S., Jouppi, N.P., Smith, J.E.: Complexity-Effective Superscalar Processor. In: Proceedings of the 24th Annual International Symposium on Computer Architecture (ISCA), pp. 206–218 (1997)
Rabaey, J.M., Chandrakasan, A., Nikolic, B.: Digital Integrated Circuits: A Design Perspective, 2nd edn. Prentice-Hall, Englewood Cliffs (2003)
Sassone, P.G., Wills, D.S.: Multi-cycle Broadcast Bypass: Too Readily Overlooked. In: Proceedings of the Workshop on Complexity-Effective Design (WCED) (May 2004)
Sassone, P.G., Wills, D.S.: Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication. In: International Symposium on Microarchitecture (MICRO), p. 717 (2004)
Stitt, G., Lysecky, R., Vahid, F.: Dynamic Hardware/Software Partitioning: A First Approach. In: Design Automation Conference (DAC), pp. 250–255 (2003)
Yehia, S., Temam, O.: From Sequences of Dependent Instructions to Functions: A Complexity-Effective Approach for Improving Performance without ILP or Speculation. In: International Symposium on Computer Architecture (ISCA), pp. 238–249 (2004)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Koh, L.W., Diessel, O. (2006). Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays. In: Jesshope, C., Egan, C. (eds) Advances in Computer Systems Architecture. ACSAC 2006. Lecture Notes in Computer Science, vol 4186. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11859802_14
Download citation
DOI: https://doi.org/10.1007/11859802_14
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-40056-1
Online ISBN: 978-3-540-40058-5
eBook Packages: Computer ScienceComputer Science (R0)