Abstract
In a system-on-a-chip embedded system, an external bus connects embedded processor cores, I/O peripherals, direct memory access (DMA) and off-chip memory. The power on the external bus makes up a significant portion of the overall power use in the system. In this paper, we will focus on the address and control bus power on the external bus. We have developed an external bus power model which monitors memory bus state transitions and models power-efficient bus arbitration schemes power. Our model allows us to consider performance/power trade-offs in managing off-chip memory accesses. We use an Analog Devices ADSP-BF533 multimedia system-on-a-chip embedded system as our target architecture to validate our model. By using more power-efficient external bus arbitration schemes, we find we can reduce overall power by as much as 18%.
An erratum to this chapter can be found at http://dx.doi.org/10.1007/11574859_13 .
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References
Benini, L., De Micheli, G., Macii, E., Sciuto, D., Silvano, C.: Address bus encoding techniques for system-level power optimization. In: Proceedings of the conference on Design, automation and test in Europe, pp. 861–867. IEEE Computer Society, Los Alamitos (1998)
Panda, P.R., Dutt, N.D.: Reducing address bus transitions for low power memory mapping. In: Proceedings of the 1996 European conference on Design and Test, vol. 63. IEEE Computer Society, Los Alamitos (1996)
Analog Devices Inc. Norwood, MA: Engineer-to-Engineer Note EE-229: Estimating Power for ADSP-BF533 Blackfin Processors, Rev 1.0 (2004)
Givargis, T.D., Vahid, F., Henkel, J.: Fast cache and bus power estimation for parameterized system-on-a-chip design. In: Proceedings of the conference on Design, automation and test in Europe, pp. 333–339. ACM Press, New York (2000)
Sotiriadis, P.P., Chandrakasan, A.: Low-power bus coding techniques considering inter-wire capacitances. In: Proceedings of IEEE Conference on Custom Integrated Circuits (CICC 2000), pp. 507–510 (2000)
Lv, T., Henkel, J., Lekatsas, H., Wolf, W.: A dictionary-based en/decoding scheme for low-power data buses. IEEE Trans. Very Large Scale Integr. Syst. 11, 943–951 (2003)
Stan, M., Burleson, W.: Bus-invert coding for low-power I/O. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 49–58 (1995)
Analog Devices Inc. Norwood, MA: ADSP-BF533 Blackfin Processor Hardware Reference, Rev 2.0 (2004)
Texas Instruments Inc. Dallas, Texas: OMAP5912 Multimedia Processor Device Overview and Architecture Reference Guide, Rev. A (2004)
Sigma Designs, Inc. Milpitas, CA: EM8400: MPEG-2 Decoder for Set-top, DVD and Streaming Applications, Rev 01.09.03 (2003)
Rubin, F.: A search procedure for hamilton paths and circuits. J. ACM 21, 576–580 (1974)
Vandersanden, S., Kaeli, D., Olivadoti, G., Gentile, R.: Developing energy-aware strategies for the blackfin processor. In: Proceedings of the Hight Performance Embedded Computing Conference (September 2004)
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Ning, K., Kaeli, D. (2005). Bus Power Estimation and Power-Efficient Bus Arbitration for System-on-a-Chip Embedded Systems. In: Falsafi, B., VijayKumar, T.N. (eds) Power-Aware Computer Systems. PACS 2004. Lecture Notes in Computer Science, vol 3471. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11574859_7
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DOI: https://doi.org/10.1007/11574859_7
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